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US 10,770,129 B2Granted
Pseudo-channeled DRAM
AssigneeIntel Corporation
InventorsHussein Alameer, Kjersten Criss, Uksong Kang
Life of this patent
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Abstract
An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.
Claims19
A memory system, comprising:
- two or more dynamic random access memory devices;
- and
- logic communicatively coupled to the two or more dynamic random access memory devices to:
- provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel;
- dedicate data pins for each of the pseudo-channels;
- and
- share command address pins between at least two of the two or more pseudo-channels.
4 more elements
A semiconductor apparatus, comprising:
- one or more substrates;
- dynamic random access memory coupled to the one or more substrates;
- and
- logic coupled to the one or more substrates and the dynamic random access memory, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
- layout the dynamic random access memory with two or more pseudo-channels per memory channel;
- and
- dedicate data pins for each of the pseudo-channels.
4 more elements
A method of organizing memory, comprising:
- providing two or more dynamic random access memory devices;
- and
- providing access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel;
- and
- sharing command address pins between at least two of the two or more pseudo-channels.
2 more elements
Dependencies are inferred from the claim text.