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US 10,770,125 B2Granted
Fixed voltage sensing in a memory device
AssigneeMicron Technology, Inc.
InventorAdam D. Johnson
Life of this patent
Estimating the term…
Abstract
Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.
Claims20
An apparatus comprising:
- a ferroelectric random access memory (FeRAM) circuit comprising:
- a ferroelectric memory cell having a first node coupled to a data line through a first access transistor and a second node coupled to a plate node of the FeRAM circuit;
- and
- a reference capacitance having a first node coupled to a reference line through a second access transistor and a second node coupled to the plate node of the FeRAM circuit;
- and
- first and second precharge transistors coupled in series between the data line and the reference line of the FeRAM circuit, the first precharge transistor having a first node coupled to the data line and a second node coupled to the plate node of the FeRAM circuit, and the second precharge transistor having a first node coupled to the reference line and a second node coupled to the plate node of the FeRAM circuit,
- wherein the plate node of the FeRAM:
- circuit is configured to hold the second nodes of the first and second precharge transistors and the first nodes of the ferroelectric memory cell and the reference capacitor at the same potential throughout sense and write operations of the ferroelectric memory cell.
5 more elements
A method comprising:
- mirroring a displacement current from a reference line to a data line using a current mirror including first and second pull up transistors having respective control gates directly coupled to the reference line,
- wherein the data line and the reference line are directly coupled between series-connected first and second precharge transistors, the first precharge transistor having a first node coupled to the data line and a second node coupled to a plate node of a ferroelectric random access memory (FeRAM) circuit, the second precharge transistor having a first node coupled to the reference line and a second node coupled to the plate node,
- wherein the FeRAM circuit comprises:
- a ferroelectric memory cell having a first node coupled to the data line through a first access transistor and a second node coupled to the plate node;
- and
- a reference capacitance having a first node coupled to the reference line through a second access transistor and a second node coupled to the plate node, and
- wherein the plate node of the FeRAM circuit is configured to hold the second nodes of the first and second precharge transistors and the first nodes of the ferroelectric memory cell and the reference capacitor at the same potential throughout sense and write operations of the ferroelectric memory cell.
4 more elements
A system comprising:
- a controller to control the system;
- and
- a ferroelectric random access memory (FeRAM) circuit coupled to the controller, the FeRAM circuit comprising:
- a ferroelectric memory cell having a first node coupled to a data line through a first access transistor and a second node directly coupled to a plate node;
- a reference capacitance having a first node coupled to a reference line through a second access transistor and a second node directly coupled to the plate node;
- an equilibrate circuit having a first node coupled to the data line and a second node coupled to the reference line, wherein the equilibrate circuit is controlled by an equilibrate signal;
- a precharge circuit coupled between the data line and the reference line, the precharge circuit comprising first and second precharge transistors coupled in series, separate from the equilibrate circuit, the first precharge transistor having a first node coupled to the data line and a second node coupled to the plate node, the second precharge transistor having a first node coupled to the reference line and a second node coupled to the plate node, the precharge circuit controlled by a precharge signal;
- and
- a current mirror circuit coupled to the data line and the reference line, the current mirror circuit comprising first and second pull up transistors having respective control gates directly coupled to the reference line, the first and second pull up transistors configured to mirror displacement current from the reference line to the data line,
- wherein the plate node of the FeRAM circuit is configured to hold the second nodes of the first and second precharge transistors and the first nodes of the ferroelectric memory cell and the reference capacitor at the same potential throughout sense and write operations of the ferroelectric memory cell.
7 more elements
Dependencies are inferred from the claim text.