Memory input hold time adjustment

A device for providing gated data signals, the device comprising:

• a delay path configured to receive an input signal and output a data signal indicative of the input signal and delayed from the input signal by a time interval;
• a gating signal generator configured to supply a gating signal;
• a gating circuit having a data input operatively connected to the delay path, a data output, and a gating input operatively connected to the gating signal generator, the gating circuit being configured to receive the data signal from the delay path at the data input, receive the gating signal at the gating input, and output at the data output an output signal indicative of the received data signal when the gating signal is present at the gating input;
• and
• a delay controller configured to receive a variable delay control signal and set the delay time interval according to the delay control signal, wherein the delay path includes a portion with a variable impedance, and wherein the delay controller is configured to vary the impedance of delay path portion.

A memory device, comprising:

• a memory cell module;
• a delay path configured to receive an input signal and output a data signal indicative of the input signal and delayed from the input signal by a delay time interval;
• a gating signal generator configured to supply a gating signal;
• a gating circuit configured to receive the data signal from the delay path, receive the gating signal, and output to the memory cell module the received data signal upon receiving the gating signal;
• and
• a delay controller configured to vary the delay time interval according to an input to the delay controller, wherein:
• the gating signal generator comprises a clock pulse generator, and the gating signal comprises a clock pulse generated by the clock pulse generator;
• the gating module comprises a gated latch;
• and
• the delay path comprises a delay element powered by a power supply and having a delay time that is dependent at least in part on the power applied to the delay element, and the delay controller is configured to vary the power applied to the delay element.

A memory device, comprising:

• a memory cell module;
• a delay path configured to receive an input signal and output a data signal indicative of the input signal and delayed from the input signal by a delay time interval;
• a gating signal generator configured to supply a gating signal;
• a gating circuit configured to receive the data signal from the delay path, receive the gating signal, and output to the memory cell module the received data signal upon receiving the gating signal;
• and
• a delay controller configured to vary the delay time interval according to an input to the delay controller, wherein:
• the gating signal generator comprises a clock pulse generator, and the gating signal comprises clock pulses generated by the clock pulse generator;
• the gating module comprises a gated latch;
• and
• the delay path includes a portion with a variable impedance, and the delay controller is configured to vary the impedance of delay path portion.

A process of writing data to a memory cell, the method comprising:

• transmitting a data signal through an input line;
• applying a gating pulse to enable a write operation inputting the transmitted data signal into a memory device;
• determining whether a performance parameter of the write operation or a length of time after an onset of the gating pulse during which length of time the transmitted data signal is stable meets one or more predetermined criteria;
• and
• adjusting a time interval by which the data signal is delayed by the input line till the performance parameter or length of time meets one or more predetermined criteria.