US 10,770,121 B1 · Memory device and memory writing method

Abstract

A memory device includes a memory array, write drivers and a controller. The memory array includes a plurality of memory units respectively arranged in a plurality of bit lines. The write drivers generate a plurality of write bit signals respectively inputted to the bit lines. The controller provides a voltage mode control signal and a current mode control signal. The controller is electrically coupled to the write drivers. Each of the write drivers generates a respective write bit signal of each of the write drivers according to the voltage mode control signal and the current mode control signal. When each of the memory units is in a set state, the controller outputs the voltage mode control signal and the current mode control signal to the write drivers. When each of the memory units is in a reset state, the controller outputs the voltage mode control signal to the write drivers.

Claims12

Dependent claims

A memory device comprising:

a memory array, comprising a plurality of memory units respectively arranged in a plurality of bit lines;
a plurality of write drivers configured to generate a plurality of write bit signals respectively input to the bit lines;
and
a controller configured to provide a voltage mode control signal and a current mode control signal, wherein the controller is electrically coupled to the write drivers;
wherein, each of the write drivers respectively generates, according to the voltage mode control signal and the current mode control signal, one of the write bit signals corresponding to each of the write drivers;
in response to each of the memory units being in a set state, the controller outputs the voltage mode control signal and the current mode control signal to the write drivers and in response to each of the memory units being in a reset state, the controller outputs the voltage mode control signal to the write drivers.

3 more elements

A memory writing method, configured to generate a plurality of write bit signals, the write bit signals being configured to write a plurality of memory units of plurality of bit lines, the memory writing method comprising:

determining the memory units to be written into a set state or a reset state;
outputting a voltage mode control signal and a current mode control signal to a plurality of write drivers in response to the memory units being required to be written into the set state, so that the write bit signals being generated by the write drivers according to the voltage mode control signal and the current mode control signal;
and outputting the voltage mode control signal in response to the memory units being required to be written into the reset state, so that the write bit signals being generated by the write drivers according to the voltage mode control signal.

Dependencies are inferred from the claim text.

Memory device and memory writing method

Life of this patent

Memory device and memory writing method

Life of this patent

Abstract

Claims12