US 10,770,119 B2Granted

Memory circuit

AssigneeMacronix International Co., Ltd.

InventorsSu-Chueh Lo, Ken-Hui Chen, Kuen-Long Chang, Ming-Chih Hsieh

Life of this patent

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Abstract

A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.

Claims10

Dependent claims

A memory circuit, having a memory cell array, and comprising:

a data receiving stage circuit, configured to receive a serial input signal and a chip enable signal;
a data writing circuit, coupled to the data receiving stage circuit, and configured to generate at least one of a command signal and a data signal according to the serial input signal;
a power supply circuit, configured to generate an operating voltage for the memory cell array to perform a data access operation;
a data output stage circuit, coupled to the memory cell array, and configured to output a readout data;
and
a controller, coupled to the data writing circuit and the power supply circuit, and configured to:
perform a switching operation of an operating state of the memory circuit according to a changing state of the chip enable signal;
and
determine a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit and the data output stage circuit according to the operating state of the memory circuit.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/534,992Filed 7 Aug 2019 · us provisional application
Priority: 6 Dec 2018
Published: US 2020/0185010 A111 Jun 2020
Granted: 8 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

G11C 5/147
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: voltage…
G11C 7/02
Arrangements for writing information into, or reading information out from, a digital store: with means for avoiding parasitic signals
G11C 5/145
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels:…
G11C 5/148
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: details…

Family

Application62/775,911Us provisional application · filed 6 Dec 2018
US 2020/0185010 A1Pre-grant publication · published 11 Jun 2020
US 10,770,119 B2This patent

From the US filing history. Foreign family members aren’t listed.

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