Semiconductor storage device

A semiconductor storage device, comprising:

• a source line, a first selection gate line, a plurality of first word lines, and a first dummy word line that are stacked one above the other in a first direction;
• a first semiconductor layer that extends in the first direction through the first selection gate line, the first word lines, and the first dummy word line and is electrically connected to the source line;
• a plurality of first memory cells at intersections of the first semiconductor layer and the first word lines;
• a connection portion contacting the first semiconductor layer and formed of an N-type diffusion layer;
• a second dummy word line, a plurality of second word lines, and a second selection gate line that are stacked one above the other in the first direction above the connection portion;
• a second semiconductor layer that extends in the first direction through the second dummy word line, the second word lines, and the second selection gate line and is electrically connected to the connection portion;
• a plurality of second memory cells at intersections of the second semiconductor layer and the second word lines;
• a bit line above the second selection gate line in the first direction and electrically connected to the second semiconductor layer;
• and
• a control circuit configured to apply during an erasing operation of the first memory cells:
• a first voltage to the source line, the first selection gate line, the second dummy word line, the second word lines, the second selection gate line, and the bit line,
• a second voltage lower than the first voltage to the first word lines, and
• a third voltage between the first voltage and the second voltage to the first dummy word line, wherein
• the connection portion includes:
• a first conductive layer extending into the first dummy word line in the first direction and being an N-type diffusion layer, and
• a second conductive layer extending into the second dummy word line in the first direction and being an N-type diffusion layer.

A semiconductor memory device, comprising:

• a plurality of word line layers stacked in a first direction;
• a dummy word line layer above the plurality of word line layers in the first direction;
• a first pillar portion extending in the first direction through the dummy word line layer and the word line layers, a first end of the first pillar portion being connected to a source line, the first pillar portion comprising a first insulating core, a first semiconductor layer on the first insulating core, and a memory film on the first semiconductor layer between the first semiconductor layer and the word line layers;
• a N-type diffusion layer portion electrically contacting the first semiconductor layer at a second end of the first pillar portion;
• a second pillar portion extending in the first direction from the N-type diffusion layer portion, the second pillar portion comprising a second insulating core, a second semiconductor layer on the second insulating core, and a stacked film on the second semiconductor layer, wherein
• the N-type diffusion layer portion extends into the second end of the first pillar portion to a position overlapping with the first dummy word line layer, and
• the second semiconductor layer is connected to the N-type diffusion layer portion.