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US 10,770,020 B2Granted
Display panel
AssigneeSamsung Display Co., Ltd.
InventorsJae-Hoon Lee, Seung-Hwan Moon, Yong-Soon Lee, Young-Su Kim, Chang-Ho Lee, Whee-Won Lee, Jun-Yong Song, Yu-Han Bae
Life of this patent
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Abstract
A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.
Claims32
A display device comprising:
- a display area including a gate line;
- a gate driver connected to an end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
- wherein a stage of the plurality of stages comprises:
- a clock input terminal to which a clock signal is input;
- a first low voltage terminal to which a first low voltage is input;
- a second low voltage terminal to which a second low voltage is input, the second low voltage being different from the first low voltage;
- a first input terminal to which at least one transmission signal from a previous stage is input;
- a gate voltage output terminal which outputs a gate signal including a gate-off voltage and a gate-on voltage;
- a first transistor including a control terminal connected to a first node, an input terminal connected to the clock input terminal, and an output terminal connected to the gate voltage output terminal;
- a third transistor including a control terminal connected to a second node, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal;
- a fifth transistor including a control terminal connected to the first input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected the second node;
- and
- a tenth transistor including a control terminal, an input terminal, and an output terminal, wherein the input terminal of the tenth transistor is connected to the second low voltage terminal, and the output terminal of the tenth transistor is connected to the first node,
- wherein a voltage level of the gate-off voltage includes the first low voltage.
11 more elements
A display device comprising:
- a display area including a gate line;
- a gate driver connected to an end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
- wherein a stage of the plurality of stages comprises:
- a clock input terminal to which a clock signal is input;
- a first low voltage terminal to which a first low voltage is input;
- a second low voltage terminal to which a second low voltage is input, the second low voltage being different from the first low voltage;
- a first input terminal to which at least one transmission signal from a previous stage is input;
- a second input terminal to which at least one transmission signal from one of next stages is input;
- a gate voltage output terminal which outputs a gate signal including a gate-off voltage and a gate-on voltage;
- a first transistor including a control terminal connected to a first node, an input terminal connected to the clock input terminal, and an output terminal connected to the gate voltage output terminal;
- a third transistor including a control terminal connected to a second node, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal;
- a sixth transistor including a control terminal connected to the second input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node;
- and
- a fifth transistor including a control terminal, an input terminal, and an output terminal, wherein the input terminal of the fifth transistor is connected to the second low voltage terminal, and the output terminal of the fifth transistor is connected to the second node,
- wherein a voltage level of the gate-off voltage includes the first low voltage.
12 more elements
A display device comprising:
- a display area including a gate line;
- a gate driver connected to an end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
- wherein a stage of the plurality of stages comprises:
- a clock input terminal to which a clock signal is input;
- a first low voltage terminal to which a first low voltage is input;
- a second low voltage terminal to which a second low voltage is input, the second low voltage being different from the first low voltage;
- a first input terminal to which at least one transmission signal from a previous stage is input;
- a gate voltage output terminal which outputs a gate signal including a gate-off voltage and a gate-on voltage;
- a first transistor including a control terminal connected to a first node, an input terminal connected to the clock input terminal, and an output terminal connected to the gate voltage output terminal;
- a third transistor including a control terminal connected to a second node, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal;
- a tenth transistor including a control terminal connected to the second node, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node;
- a transmission signal output terminal which outputs a transmission signal of the stage;
- and
- an eleventh transistor including a control terminal connected to the second node, an input terminal connected to the transmission signal output terminal, and an output terminal connected to the second low voltage terminal,
- wherein a voltage level of the gate-off voltage includes the first low voltage.
12 more elements
A display device comprising:
- a display area including a gate line;
- a gate driver connected to an end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
- wherein a stage of the plurality of stages comprises:
- a clock input terminal to which a clock signal is input;
- a first low voltage terminal to which a first low voltage is input;
- a second low voltage terminal to which a second low voltage is input, the second low voltage being different from the first low voltage;
- a first input terminal to which at least one transmission signal from a previous stage is input;
- a second input terminal to which at least one transmission signal from one of next stages is input;
- a gate voltage output terminal which outputs a gate signal including a gate-off voltage and a gate-on voltage;
- a first transistor including a control terminal connected to a first node, an input terminal connected to the clock input terminal, and an output terminal connected to the gate voltage output terminal;
- a third transistor including a control terminal connected to a second node, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal;
- and
- a sixth transistor including a control terminal connected to the second input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node;
- and
- wherein a voltage level of the gate-off voltage includes the first low voltage, and
- wherein the voltage level of the second node includes the second low voltage.
13 more elements
A display device comprising:
- a display area including a gate line;
- a gate driver connected to an end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
- wherein a stage of the plurality of stages comprises:
- a clock input terminal to which a clock signal is input;
- a first low voltage terminal to which a first low voltage is input;
- a second low voltage terminal to which a second low voltage is input, the second low voltage being different from the first low voltage;
- a first input terminal to which at least one transmission signal from a previous stage is input;
- a gate voltage output terminal which outputs a gate signal including a gate-off voltage and a gate-on voltage;
- a first transistor including a control terminal connected to a first node, an input terminal connected to the clock input terminal, and an output terminal connected to the gate voltage output terminal;
- a third transistor including a control terminal connected to a second node, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal;
- and
- a tenth transistor including a control terminal connected to the second node, an input terminal connected to the second low voltage terminal, and an output terminal connected to the first node,
- wherein a voltage level of the gate-off voltage includes the first low voltage, and
- wherein the voltage level of the second node includes the second low voltage.
11 more elements
Dependencies are inferred from the claim text.