Shift register circuit, driving method thereof, gate driver and display panel

A shift register circuit comprising:

• an input terminal configured to receive an input pulse;
• a reset terminal configured to receive a reset pulse;
• a first scan voltage terminal configured to be applied with a first scan voltage;
• a second scan voltage terminal configured to receive a second scan voltage;
• a first reference voltage terminal configured to receive a first reference voltage;
• a second reference voltage terminal configured to receive a second reference voltage;
• a clock terminal configured to receive a clock signal;
• an output terminal configured to output an output signal;
• an input circuit configured to supply the first scan voltage to a first node in response to the input pulse received at the input terminal being active, and to supply the second scan voltage to the first node in response to the reset pulse received at the reset terminal being active;
• a first control circuit configured to bring the first reference voltage terminal into conduction with a second node in response to the first reference voltage applied at the first reference voltage terminal being active, to bring the second reference voltage terminal into conduction with the second node in response to the first node being at an active potential, to supply the second reference voltage applied at the second reference voltage terminal to the first node, and bring the second reference voltage terminal into conduction with the output terminal in response to the second node being at the active potential;
• a second control circuit configured to bring the second reference voltage terminal into conduction with a third node in response to the second reference voltage applied at the second reference voltage terminal being active, to bring the first reference voltage terminal into conduction with the third node in response to the first node being at the active potential, and to supply the first reference voltage applied at the first reference voltage terminal to the first node and bring the first reference voltage terminal into conduction with the output terminal in response to the third node being at the active potential;
• and
• an output circuit configured to bring the clock terminal into conduction with the output terminal in response to the first node being at the active potential.