Alternate-logic head-to-head gate driver on array
AssigneeApple Inc.
InventorsRungrot Kitsomboonloha, Szu-Hsien Lee
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Abstract
The disclosure is related to head-to-head (H2H) gate on arrays (GOA) for pixel-based displays that may have reduced dimensions. In the described embodiments, the H2H design with alternate logic may be used to drive groups of pixels (e.g., a pixel row or column) with a primary and a secondary driver, located in opposite ends of the bezel of the electronic device. In the alternate-logic design, a shared shift-register may be used to enable two rows or columns. Embodiments in which more than two rows or columns are controlled by a single shift register are also described.
Claims21
An electronic device comprising:
- a display comprising:
- a pixel array comprising a plurality of pixel groups;
- and
- gate on array circuitry comprising:
- a first driver configured to receive a first clock signal and a first gate-enable signal, and provide a first driving output to a first pixel group of the plurality of pixel groups;
- a second driver configured to receive a second clock signal and the first gate-enable signal, and provide a second driving output to a second pixel group of the plurality of pixel groups;
- a bootstrapping capacitor coupled to the first driver and the second driver, wherein the bootstrapping capacitor is configured to facilitate operations of the first driver and the second driver;
- and
- a first shift register configured to generate the first gate-enable signal.
A display comprising:
- a display portion comprising at least a first pixel row, a second pixel row, and a third pixel row;
- and
- a bezel disposed along a periphery of the display portion, wherein the bezel comprises a first bezel portion and a second bezel portion located on an opposite side of the bezel relative to the first bezel portion;
- first gate on array (GOA) circuitry disposed in the first bezel portion, wherein the first GOA circuitry comprises a first plurality of logic units, wherein at least a first logic unit of the first plurality of logic units is configured to drive the first pixel row;
- and
- second GOA circuitry disposed in the second bezel portion, wherein the second GOA circuitry comprises a second plurality of logic units, wherein at least a second logic unit of the second plurality of logic units is configured to drive the third pixel row, and wherein at least the first logic unit of the first GOA and at least the second logic unit of the second GOA are configured to drive the second pixel row.
A display comprising:
- a pixel array comprising a plurality of pixel rows;
- and
- a bezel disposed along a periphery of the pixel array, wherein the bezel comprises a first bezel portion that comprises a first bezel length;
- and
- first gate on array circuitry disposed in the first bezel portion, wherein the first gate on array circuitry comprises a plurality of logic units, wherein each logic unit of the plurality of logic units comprises a shift register coupled to a primary driver and a secondary driver;
- wherein the first bezel length comprises a gate on array length and the gate on array length comprises a percentage of the first bezel length that is smaller than a threshold percentage, and wherein at least one pixel row is coupled to a respective primary driver of the first gate on array circuitry and a respective secondary driver of a second gate on array circuitry.
Dependencies are inferred from the claim text.