Shift register and driving method of the same, emission driving circuit, and display device

A driving method of an emission driving circuit, applicable in an emission driving circuit comprising:

• a first node control module electrically connected to an input signal terminal, a first clock signal terminal, a second clock signal terminal and a high level signal terminal, and configured to provide an input signal or a high level signal to a first node based on a first clock signal and a second clock signal, so as to control a level at the first node;
• a second node control module electrically connected to the first node, the first clock signal terminal, the second clock signal terminal, a first low level signal terminal and the high level signal terminal, and configured to control a level at a second node based on the level at the first node, the first clock signal, the second clock signal, a first low level signal and the high level signal;
• an output control module electrically connected to the first node, the second node, the high level signal terminal and a second low level signal terminal, and configured to control an output terminal to output a high level or a low level based on the level at the first node, the level at the second node, the high level signal and a second low level signal;
• and
• a carry control module electrically connected to the second node, the high level signal terminal, the output terminal and the second low level signal terminal, and configured to control a carry terminal to output a high level or a low level based on the level at the second node, a level at the output terminal, the high level signal and the second low level signal,
• wherein the output control module comprises a ninth transistor, a tenth transistor;
• the carry control module comprises an eleventh transistor and a twelfth transistor,
• wherein the ninth transistor has a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal, and a second terminal electrically connected to the output terminal,
• the tenth transistor has a control terminal electrically connected to the first node, a first terminal electrically connected to the second low level signal terminal and a second terminal electrically connected to the output terminal,
• wherein the eleventh transistor has a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal, and a second terminal electrically connected to the carry terminal, and
• the twelfth transistor has a control terminal electrically connected to the output terminal, a first terminal electrically connected to the second low level signal terminal and a second terminal electrically connected to the carry terminal,
• wherein the driving method comprises:
• providing, by the first node control module, a high level at the first node;
• maintaining, by the second node control module, the second node at a high level in a previous phase;
• maintaining, by the output control module, the output terminal at a low level outputted in a previous phase based on the high level at the first node and the high level at the second node;
• and controlling, by the carry control module, the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal, in a first phase when the input signal provided by the input signal terminal is at a high level, the first clock signal provided by the first clock signal terminal is at a low level, and the second clock signal provided by the second clock signal terminal is at a high level,
• providing, by the first node control module, a high level at the first node;
• providing, by the second node control module, a low level at the second node;
• controlling, by the output control module, the output terminal to output a high level based on the high level at the first node and the low level at the second node;
• and controlling, by the carry control module, the carry terminal to output a high level based on the low level at the second node and the high level at the output terminal, in a second phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a high level, and the second clock signal provided by the second clock signal terminal is at a low level,
• providing, by the first node control module, a low level at the first node;
• providing, by the second node control module, a high level at the second node;
• controlling, by the output control module, the output terminal to output a low level based on the low level at the first node and the high level at the second node;
• and controlling, by the carry control module, the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal, in a third phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a low level, the second clock signal provided by the second clock signal terminal is at a high level, and
• providing, by the first node control module, a low level at the first node;
• providing, by the second node control module, a high level at the second node;
• controlling, by the output control module, the output terminal to output a low level based on the low level at the first node and the high level at the second node;
• and controlling, by the carry control module, the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal, in a fourth phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a high level, the second clock signal provided by the second clock signal terminal is at a low level.