Single input multiple data processing mechanism

A processing apparatus, comprising:

• a graphics processing unit (GPU), including:
• a register file having a plurality of channels to store data, the plurality of channels including a first channel to store first data for an instruction to be executed by a processing resource and a second channel to store second data for the instruction to be executed by the processing resource;
• and
• a processing resource to:
• examine the first data and the second data and upon a determination that the first data and the second data are the same, to:
• read the first data from the first channel of the plurality of channels;
• and
• generate a scoreboard value to be stored in a scoreboard communicatively coupled to the processing resource, wherein the first scoreboard value indicates that the first data and the second data are the same;
• and
• in response to a determination that the instruction to be executed by the processing resource comprises at least a first source and a second source, to:
• perform a logical operation on a first scoreboard value associated with the first source and a second scoreboard value associated with the second source to produce a destination scoreboard value;
• write the first data value to the second channel in response to a determination that the destination scoreboard value indicates that first scoreboard value and the second scoreboard value are equal;
• generate a flag signal upon a determination that each of the plurality of channels has the same data;
• store the flag signal as a scoreboard value, wherein the scoreboard value is accessed upon received a SIMD instruction to be processed by the processing resource;
• in response to a determination that the instruction is a one source instruction, retrieve the scoreboard value from the scoreboard as a source scoreboard value and copy the scoreboard value to a destination address in the scoreboard as a destination scoreboard value;
• and
• write a data value resulting from the execution of the instruction to the second channel,
• wherein two or more scoreboard values are retrieved from the scoreboard as source scoreboard values upon a determination that the instruction is not a one source instruction, a logical operation is performed on the two or more scoreboard values and a result of the logic is stored in a destination address in the scoreboard as a destination scoreboard value, and the data value in the first channel of the register file is written to the second channel upon a determination that the destination scoreboard value indicates that the two or more scoreboard values have the same value.