Clock tree optimization by moving instances toward core route

A method comprising:

• accessing an integrated circuit design stored in memory, the integrated circuit design comprising a clock tree comprising one or more routes that interconnect terminals of a plurality of clock tree instances, a clock tree instance of the plurality of clock tree instances comprising a first terminal and a second terminal;
• identifying a portion of a route in the clock tree that has a maximum transitive fanout that is less than a transitive fanout threshold, the transitive fanout threshold comprising a threshold number of terminals connected to a branch in the route;
• determining, by at least one hardware processor, a first offset based on a distance between the first terminal of the clock tree instance and the identified portion of the route in the clock tree;
• determining, by at least one hardware processor, a second offset based on a distance between the second terminal of the clock tree instance and the identified portion of the route;
• determining, by at least one hardware processor, a target offset based on a combination of the first and second offsets;
• moving, by the at least one hardware processor, the clock tree instance toward the identified portion of the route by the target offset;
• and
• generating, by at least one hardware processor, an updated clock tree for the integrated circuit design based on moving the clock tree instance toward the identified portion of the route.

A computer-storage medium storing instructions, which when executed by the machine, cause the machine to perform operations comprising:

• accessing an integrated circuit design stored in memory, the integrated circuit design comprising a clock tree comprising one or more routes that interconnect terminals of a plurality of clock tree instances, a clock tree instance of the plurality of clock tree instances comprising a first terminal and a second terminal;
• identifying a portion of a route in the clock tree based on a wirelength threshold;
• determining a first offset based on a distance between the first terminal of the clock tree instance and a the route in the clock tree;
• determining a second offset based on a distance between the second terminal of the clock tree instance and the identified portion of the route;
• determining a target offset based on a combination of the first and second offsets;
• moving the clock tree instance toward the identified portion of the route by the target offset;
• generating an updated clock tree based on moving the clock tree instance toward the identified portion of the route;
• and
• generating a layout instance for the integrated circuit design based in part on the updated clock tree, the layout instance describing physical layout dimensions of the integrated circuit design.