US 10,769,344 B1 · Determining timing paths and reconciling topology in a superconducting circuit design

Abstract

Systems and methods for determining timing paths and reconciling topology in a superconducting circuit design are provided. The design may include a first timing path having a first set of timing pins associated with a first timing constraint group including a first timing endpoint and a second timing endpoint. An example method includes processing the first timing constraint group to assign a first legal start time to the first timing endpoint and a second legal start time to the second timing endpoint. The method further includes inserting a first shadow element representing a first physically connected component on the timing path, where the first shadow element precedes the first timing endpoint or follows the second timing endpoint. The method further includes addressing any changes to the first legal start time or the second legal start time caused by an insertion of the first shadow element on the timing path.

Claims20

Dependent claims

A method, implemented by a processor, for determining timing paths and reconciling topology in a superconducting circuit design, wherein the superconducting circuit design comprises a first timing path including a first set of timing pins, and wherein a first subset of the first set of timing pins is associated with a first timing constraint group including a first timing endpoint and a second timing endpoint, the method comprising:

using the processor, processing the first timing constraint group to assign a first legal start time to the first timing endpoint and a second legal start time to the second timing endpoint;
inserting a first shadow element representing a first physically connected component on the timing path, wherein the first shadow element precedes the first timing endpoint or follows the second timing endpoint;
and
addressing any changes to the first legal start time or the second legal start time caused by an insertion of the first shadow element on the timing path.

1 more element

A method, implemented by a processor, for determining timing paths and reconciling topology in a superconducting circuit design, wherein the superconducting circuit design comprises a first timing path including a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each of the first circuit component and the second circuit component comprises Josephson junctions, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase, the method comprising:

using the processor, determining a first legal start time for the first timing endpoint on the timing path and determining a second legal start time for the second timing endpoint on the timing path;
inserting a first shadow element representing a first physically connected component on the timing path, wherein the first shadow element precedes the first circuit component on the timing path;
inserting a second shadow element representing a second physically connected component on the timing path, wherein the second shadow element follows the second circuit component on the timing path;
and
addressing any changes to the first legal start time and the second legal start time caused by an insertion of the first shadow element and the second shadow element on the timing path.

2 more elements

A system configured to determine timing paths and reconcile topology in a superconducting circuit design, wherein the superconducting circuit design comprises a first timing path including a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each of the first circuit component and the second circuit component comprises Josephson junctions, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase, the system comprising:

a processor;
and
a memory comprising instructions configured to:
determine a first legal start time for the first timing endpoint on the timing path and determine a second legal start time for the second timing endpoint on the timing path,
insert a first shadow element representing a first physically connected component on the timing path, wherein the first shadow element precedes the first circuit component on the timing path,
insert a second shadow element representing a second physically connected component on the timing path, wherein the second shadow element follows the second circuit component on the timing path, and
address any changes to the first legal start time and the second legal start time caused by an insertion of the first shadow element and the second shadow element on the timing path.

4 more elements

Dependencies are inferred from the claim text.

Determining timing paths and reconciling topology in a superconducting circuit design

Life of this patent

Determining timing paths and reconciling topology in a superconducting circuit design

Life of this patent

Abstract

Claims20