Pin access hybrid cell height design

A method of generating a layout diagram for an integrated circuit, the method comprising:

• arranging a plurality of first cells having a first cell height in a plurality of first rows;
• arranging a plurality of second cells having a second cell height less than the first cell height in a plurality of second rows, wherein the plurality of first rows and the plurality of second rows are laid out according to a routing grid comprising a plurality of first routing tracks extending in a first direction and a plurality of second routing tracks extending in a second direction perpendicular to the first direction;
• placing a plurality of first cell pins over a plurality of selected first via placement points in each first cell of the plurality of first cells, wherein each first cell pin of the plurality of first cell pins extends along a corresponding second routing track of the plurality of second routing track and has both ends terminated within top and bottom boundaries of a corresponding first cell of the plurality of first cells;
• and
• placing a plurality of second cell pins over a plurality of selected via placement points in each second cell of the plurality of second cells, wherein at least one second cell pin of the plurality of second cell pins extends along a corresponding second routing track of the plurality of second routing tracks across a boundary of a corresponding second cell of the plurality of second cells and into a corresponding first cell of the plurality of first cells abutting the corresponding second cell.

A system for processing a layout diagram for an integrated circuit, comprising:

• at least one processor;
• and
• a computer readable storage medium connected to the at least one processor, wherein the at least one processor is configured to execute instructions stored on the computer readable storage medium to:
• arrange a plurality of first cells having a first cell height in a plurality of first rows;
• arrange a plurality of second cells having a second cell height less than the first cell height in a plurality of second rows, wherein the plurality of first rows and the plurality of second rows are laid out according to a routing grid comprising a plurality of first routing tracks extending in a first direction and a plurality of second routing tracks extending in a second direction perpendicular to the first direction;
• place a plurality of first cell pins within each first cell of the plurality of first cells, wherein each of the plurality of first cell pins extends along a corresponding second routing track of the plurality of second routing tracks;
• identify a plurality of via placement points in each second cell of the plurality of second cells at corresponding intersections of a plurality of intersections between the plurality of the first routing tracks and the plurality of second routing tracks;
• select a subset of via placement points from the plurality of via placement points, wherein the subset of via placement points correspond to a set of second routing tracks in the plurality of second routing tracks along which a plurality of second cell pins for each second cell of the plurality of second cells is placed, wherein a second cell pin of the plurality of second cell pins may be placed on a same second routing track with an adjacent first cell pin of the plurality of first cell pins if none or only one first cell of a pair of first cells of the plurality of first cells immediately abutting opposite boundaries of a corresponding second cell of the plurality of second cells includes a first cell pin;
• and
• place the plurality of second cell pins over the subset of the via placement points.