US 10,769,335 B1Granted

System and method for graph based verification of electronic circuit design

AssigneeNXP USA, Inc.

InventorsPushkar Sareen, Abinash, Piyush Pandey

Life of this patent

Estimating the term…

Loading patent…

Abstract

An electronic design automation (EDA) tool for executing topological and functional checks on an electronic circuit design (ECD) includes a processor and a memory that stores the ECD, graphical rules, and filter rules for executing the checks. The processor generates a test graph based on the ECD, replaces stretchable nodes with nested networks in the test graph to generate extended graphs, and decouples real edges and functional edges of each extended graph to generate real graphs and functional graphs, respectively. Based on the graphical rules, the processor executes the topological checks on an input graph of the ECD to identify real sub-graphs from the input graph that are isomorphic to a real graph. The processor further generates functional sub-graphs by combining a functional graph with each real sub-graph, and based on the filter rules, further executes the functional checks on the functional sub-graphs to identify output graphs.

Claims20

Dependent claims

An electronic design automation (EDA) tool for executing topological and functional checks on an electronic circuit design, the EDA tool comprising:

a memory that is configured to store the electronic circuit design, a set of graphical rules, and a set of filter rules for executing the topological and functional checks;
and
a processor that communicates with the memory, wherein the processor is configured to:
generate a test graph based on the electronic circuit design, wherein the test graph comprises a first set of normal nodes, a set of stretchable nodes, a first set of real edges, and a first set of functional edges;
replace the set of stretchable nodes with a set of nested networks in the test graph to generate a set of extended graphs, wherein each extended graph comprises the first set of normal nodes, the set of nested networks, a second set of real edges, and a second set of functional edges;
decouple the second set of real edges and the second set of functional edges of each extended graph to generate a set of real graphs and a set of functional graphs, respectively;
execute the topological checks on an input graph of the electronic circuit design, based on the set of graphical rules, to identify a set of real sub-graphs from the input graph, wherein each real sub-graph is isomorphic to a first real graph of the set of real graphs;
generate a set of functional sub-graphs by combining a first functional graph of the set of functional graphs with each real sub-graph;
and
execute the functional checks on the set of functional sub-graphs, based on the set of filter rules, to identify a set of output graphs.

7 more elements

A method for executing topological and functional checks on an electronic circuit design by using an electronic design automation (EDA) tool, wherein the EDA tool includes a memory and a processor in communication with the memory, and wherein the memory stores the electronic circuit design, a set of graphical rules, and a set of filter rules for executing the topological and functional checks, the method comprising:

generating a test graph based on the electronic circuit design, wherein the test graph comprises a first set of normal nodes, a set of stretchable nodes, a first set of real edges, and a first set of functional edges;
replacing the set of stretchable nodes with a set of nested networks in the test graph to generate a set of extended graphs, wherein each extended graph comprises the first set of normal nodes, the set of nested networks, a second set of real edges, and a second set of functional edges;
decoupling the second set of real edges and the second set of functional edges of each extended graph to generate a set of real graphs and a set of functional graphs, respectively;
executing the topological checks on an input graph of the electronic circuit design, based on the set of graphical rules, to identify a set of real sub-graphs from the input graph, wherein each real sub-graph is isomorphic to a first real graph of the set of real graphs;
generating a set of functional sub-graphs by combining a first functional graph of the set of functional graphs with each real sub-graph;
and
executing the functional checks on the set of functional sub-graphs, based on the set of filter rules, to identify a set of output graphs.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/667,748Filed 29 Oct 2019
Granted: 8 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F 30/30
Computer-aided design [CAD]: circuit design
G06F 2111/20
Details relating to CAD techniques: configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned…
G06F
Computing and data processing

Family

No related US applications are recorded in the indexed filing history.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key