Intelligent fail recognition

A computer program product comprising:

• a non-transitory computer-readable storage medium having program instructions embodied therewith for debugging one or more simulation fails in processor design verification, the program instructions executable by one or more processors, the program instructions including:
• determining whether a prediction model to predict one or more bug labels for the one or more simulation fails in a processor design exists;
• retrieving, in response to determining the prediction model exists, the prediction model;
• predicting one or more bug labels for the one or more simulation fails in the processor design using the prediction model;
• determining whether a fix is available for the one or more predicted bug labels;
• and
• simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels in the processor design.

A fail recognition apparatus for debugging one or more simulation fails in processor design verification, the fail recognition apparatus comprising:

• memory having program instructions embodied therewith, and
• at least one processor configured to read the program instructions to execute:
• a simulation environment configured to determine whether a prediction model to predict one or more bug labels for the one or more simulation fails in a processor exists;
• a model predictor configured to, in response to determining the prediction model exists, retrieve the prediction model and predict one or more bug labels for the one or more simulation fails in the processor design using the prediction model;
• and
• a feedback unit configured to determine whether a fix is available for the one or more predicted bug labels, and simulate, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels in the processor design.