System, method, and computer program product for debugging one or more observable failures in a formal verification
AssigneeCadence Design Systems, Inc.
InventorsMaayan Ziv, Nizar Hanna, Sanaa Halloun
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AssigneeCadence Design Systems, Inc.
InventorsMaayan Ziv, Nizar Hanna, Sanaa Halloun
Estimating the term…
The present disclosure relates to a method for electronic design verification. Embodiments may include providing, using a processor, an electronic design and determining one or more design violations based upon, at least in part, a structural observability filter. Embodiments may also include generating a violation trace based upon, at least in part, the one or more design violations and displaying the violation trace at a graphical user interface configured to allow a user to debug the one or more design violations. Embodiments may further include allowing the user to select at least one path to be waived at the graphical user interface and generating a new violation trace without the at least one path to be waived.
A computer-implemented method for electronic design verification comprising:
A non-transitory computer-readable storage medium for electronic design verification, the computer-readable storage medium having stored thereon instructions that when executed by a machine result in one or more operations, the operations comprising:
A system for electronic design verification comprising:
Dependencies are inferred from the claim text.