US 10,769,329 B1Granted

Retention model with RTL-compatible default operating mode

AssigneeSynopsys, Inc.

InventorsHarsh Chilwal, Stephen T. Scherr, Todd M. Buzan

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Abstract

A retention model includes a sequential block including two flip-flop/latch elements and a signal routing circuit having a network of alternative signal paths controlled by path control signals, which are generated by a retention controller block. The signal routing circuit enters a default operating mode when the signal path control signals are de-asserted, whereby the retention model implements a standard flip-flop/latch functionality in response to generic UPF signals applied to the model's generic input nodes, thereby facilitating RTL simulation of the retention model using a Verilog original always command. A selected retention strategy is implemented by modifying a retention controller block to assert a selected combination of path control signals, whereby the retention model may be implemented during UPF simulation using a map_retention_cell command. Restrictions prevent modification of the sequential block and path control signals and prevent use of generic input signals by the retention controller block.

Claims17

Dependent claims

A non-transitory computer readable medium comprising stored instructions, the stored instructions when executed by a processor, cause the processor to execute operations including:

model, by a retention model, a state retention cell in a circuit design, the retention model including a data input node, a clock node and a set/reset node configured to receive corresponding generic input signals from upstream circuitry of said circuit design, and a data output node configured to pass a generic output signal to downstream circuitry of said circuit design, the retention model comprising:
a sequential block including:
a storage element configured to store a first data value,
a retention element configured to store a second data value, and
a signal routing circuit operably coupled to the storage element, the retention element, the input node, the clock node, the set/reset node and the data output node;
and
a retention controller block including a signal path control circuit configured to assert one or more signal path control signals in response to one or more external retention control signals,
wherein the signal routing circuit is configured to enter a default operating mode when said retention controller block de-asserts all of said signal path control signals such that said signal routing circuit forms a first data signal path between the input terminal of the storage element and the data input node of the retention model, forms a second data signal path between the output terminal of the storage element and the data output node of the retention model, forms a clock signal path between a clock terminal of the storage element and the clock node of the retention model, and forms a set/reset signal path between a set/reset terminal of the storage element and the set/reset node of the retention model, whereby said storage element is operably configured to implement one of a flip-flop and a latch when said signal routing circuit is in said default operating mode.

5 more elements

A computer-implemented method for incorporating a state retention cell between upstream circuitry and downstream circuitry of a circuit design, the method including

instantiating a retention model into the circuit design such that a data input node of said retention model is configured to receive a generic input data signal from said upstream circuitry, such that a data output node of said retention model is configured to pass a generic output signal to downstream circuitry, and such that a clock node and a set/reset node are operably coupled to respectively receive generic clock and set/reset signals from corresponding circuitry of said circuit design,
wherein the retention model comprises:
a sequential block including
a storage element configured to store a first data value,
a retention element configured to store a second data value, and
a signal routing circuit operably coupled to the storage element, the retention element, the input node, the clock node, the set/reset node and the data output node;
and
a retention controller block including a signal path control circuit configured to assert one or more signal path control signals in response to one or more external retention control signals, and
wherein the signal routing circuit is configured to enter a default operating mode when said retention controller block de-asserts all of said signal path control signals such that said signal routing circuit forms a first data signal path between the input terminal of the storage element and the data input node of the retention model, forms a second data signal path between the output terminal of the storage element and the data output node of the retention model, forms a clock signal path between a clock terminal of the storage element and the clock node of the retention model, and forms a set/reset signal path between a set/reset terminal of the storage element and the set/reset node of the retention model, whereby said storage element is operably configured to implement one of a flip-flop and a latch when said signal routing circuit is in said default operating mode.

6 more elements

A system for incorporating a state retention cell between upstream circuitry and downstream circuitry of a circuit design, comprising:

a storage device to store a retention model;
a processing device to instantiate the retention model into the circuit design such that a data input node of said retention model is configured to receive a generic input data signal from said upstream circuitry, such that a data output node of said retention model is configured to pass a generic output signal to downstream circuitry, and such that a clock node and a set/reset node are operably coupled to respectively receive generic clock and set/reset signals from corresponding circuitry of said circuit design,
wherein the retention model includes:
a sequential block including
a storage element configured to store a first data value,
a retention element configured to store a second data value, and
a signal routing circuit operably coupled to the storage element, the retention element, the input node, the clock node, the set/reset node and the data output node;
and
a retention controller device including a signal path control circuit configured to assert one or more signal path control signals in response to one or more external retention control signals, and
wherein the signal routing circuit is configured to enter a default operating mode when said retention controller device de-asserts all of said signal path control signals such that said signal routing circuit forms a first data signal path between the input terminal of the storage element and the data input node of the retention model, forms a second data signal path between the output terminal of the storage element and the data output node of the retention model, forms a clock signal path between a clock terminal of the storage element and the clock node of the retention model, and forms a set/reset signal path between a set/reset terminal of the storage element and the set/reset node of the retention model, whereby said storage element is operably configured to implement one of a flip-flop and a latch when said signal routing circuit is in said default operating mode.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/374,385Filed 3 Apr 2019
Granted: 8 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F 30/337
Circuit design at the digital level: design optimisation
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking

Family

No related US applications are recorded in the indexed filing history.

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