Apparatus and method for reducing latency of input/output transactions in an information handling system using no-response commands

A method, comprising:

• issuing, by a system memory, a command response;
• directing, by a processor, the command response issued by the system memory intercepting, by an accelerator, the command response from the processor;
• based on an attribute of the command response, distinguishing, by the accelerator, a correct drive from an incorrect drive;
• mapping, by the accelerator, an address of the command response and sending the command response to the correct drive;
• sending, by the accelerator, a no-response command to the incorrect drive;
• receiving, from the incorrect drive, a completion and interrupt response including encoded information in reserved bits of the interrupt;
• and
• based on the encoded information in the reserved bits of the interrupt,
• discarding, by the accelerator, the completion and interrupt response to prevent the processor from processing the completion and interrupt response from the incorrect drive.

An information handling system, comprising:

• a system memory that is configured to issue a command response in response to a single command fetch;
• a processor coupled to the system memory, the processor to direct a command response issued by the system memory;
• and
• an accelerator coupled to the system memory, the accelerator configured to:
• intercept the command response from the processer;
• distinguish a correct drive from an incorrect drive based on an attribute of the command response;
• map an address of the command response and send the command response to the correct drive;
• send a no-response command to the incorrect drive;
• wherein the correct drive is configured to complete the command response, and the incorrect drive is configured to issue a response completion and interrupt response including encoded information in reserved bits of the interrupt;
• receive the completion and interrupt response;
• and
• based on the encoded information in the reserved bits of the interrupt, discard the completion and interrupt response to prevent the processor from processing the completion and interrupt response from the incorrect drive.