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US 10,769,083 B2Granted
Source synchronized signaling mechanism
AssigneeIntel Corporation
InventorsAltug Koker, Joydeep Ray, Vasanth Ranganathan, Abhishek R. Appu
Life of this patent
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Abstract
An apparatus to facilitate source synchronous signaling is disclosed. The apparatus includes transfer protocol logic to provide for source synchronous transfer of data within an interconnect fabric, including one or more synchronizers having logic to a transmit data signal and a source clock (clk) signal during the transfer of data.
Claims19
An apparatus comprising:
- an interconnect fabric including:
- a plurality of network interfaces for connection of the interconnect fabric to a plurality of nodes, each network interface including a set of one or more synchronizers, and
- a plurality of network switches to route data transfers between the plurality of network interfaces;
- wherein the interconnect fabric is to provide for source synchronous transfer of data within the interconnect fabric between a plurality of nodes connected to the plurality of network interfaces, the plurality of nodes including a plurality of compute nodes and a global shared memory for the plurality of compute nodes, wherein:
- a first network interface of the plurality of network interfaces is to transmit a data signal and a source clock signal from a first node of the plurality of nodes, and
- a second network interface of the plurality of network interfaces is to receive the data signal and the source clock signal for a second node of the plurality of nodes, wherein the second network interface is to sample and filter the data signal based on a clock domain associated with the source clock signal.
3 more elements
A system comprising:
- a plurality of compute nodes;
- a global shared memory for the plurality of compute nodes;
- and
- an interconnect fabric including:
- a plurality of network interfaces for connection of the interconnect fabric to a plurality of nodes, the plurality of nodes including the plurality of compute nodes and the global shared memory, each network interface including a set of one or more synchronizers, and
- a plurality of network switches to route data transfers between the plurality of network interfaces;
- wherein the interconnect fabric is to provide for source synchronous transfer of data within the interconnect fabric between the plurality of nodes, wherein:
- a first network interface of the plurality of network interfaces is to transmit a data signal and a source clock signal from a first node of the plurality of nodes, and
- a second network interface of the plurality of network interfaces is to receive the data signal and the source clock signal for a second node of the plurality of nodes, wherein the second network interface is to sample and filter the data signal based on a clock domain associated with the source clock signal.
6 more elements
A method comprising:
- receiving a data signal and a source clock signal from a first node of a plurality of nodes at a first network interface of an interconnect fabric;
- transmitting the data signal and the source clock signal across the interconnect fabric;
- receiving the data signal and the source clock signal at a second network interface for a second node of the plurality of nodes;
- and
- sampling and filtering the data signal at the second network interface based on a clock domain associated with the source clock signal, wherein the interconnect fabric to provide for source synchronous transfer of the data signal within the interconnect fabric;
- wherein the plurality of nodes includes a plurality of compute nodes and a global shared memory, and wherein each of the first network interface and second network interface include a set of one or more synchronizers.
3 more elements
Dependencies are inferred from the claim text.