Bandwidth-based selective memory channel connectivity on a system on chip

A method for managing memory channel connectivity on a system on chip (SoC), the method comprising:

• connecting a first memory client on a system on chip (SoC) to each of a plurality of memory channels;
• connecting a second memory client on the SoC to only a portion of the plurality of memory channels;
• the first memory client initiating a memory transaction involving shared memory with the second memory client;
• receiving a physical address for the memory transaction;
• and
• translating the physical address to divert memory traffic to only the portion of the plurality of memory channels to which the second memory client is connected.

A system for managing memory channel connectivity on a system on chip (SoC), the system comprising:

• means for connecting a first memory client on a system on chip (SoC) to each of a plurality of memory channels and a second memory client on the SoC to only a portion of the plurality of memory channels;
• means for receiving a physical address for a memory transaction generated by the first memory client and involving a shared page with the second memory client;
• and
• means for translating the physical address to divert memory traffic to only the portion of the plurality of memory channels to which the second memory client is connected.

A computer program embodied in a non-transitory computer readable medium and executed by a processor, the computer program for managing memory channel connectivity on a system on chip (SoC) comprising a first memory client and a second memory client, the computer program comprising logic configured to:

• receive a physical address for a memory transaction generated by the first memory client and involving a shared page with the second memory client, the first memory client connected to each of a plurality of memory channels and the second memory client connected to only a portion of the plurality of memory channels;
• determine one or more descriptors in a page table for the shared page that specify the portion of the plurality of memory channels to which the second memory client is connected;
• and
• modify the physical address to divert memory traffic to only the portion of the plurality of memory channels to which the second memory client is connected.