US 10,769,062 B2 · Fine granularity translation layer for data storage devices

Abstract

A Data Storage Device (DSD) includes a non-volatile memory configured to store data, and control circuitry configured to receive a memory access command from a host to access data in the non-volatile memory. A location is identified in the non-volatile memory for performing the memory access command using an Address Translation Layer (ATL) that has a finer logical-to-physical granularity than a logical-to-physical granularity of a logical block-based file system executed by the host or a granularity based on a memory Input/Output (IO) transaction size of a processor of the host. The non-volatile memory is accessed at the identified location to perform the memory access command.

Claims21

Dependent claims

A Data Storage Device (DSD), comprising:

a non-volatile memory configured to store data;
and
control circuitry configured to:
receive a memory access command from a host to access data in the non-volatile memory;
identify a location in the non-volatile memory for performing the memory access command using an Address Translation Layer (ATL) that has a finer logical-to-physical granularity than a logical-to-physical granularity of a logical block-based file system executed by the host;
and
access the non-volatile memory at the identified location to perform the memory access command.

4 more elements

A non-transitory computer readable medium storing computer-executable instructions, wherein when the computer-executable instructions are executed by control circuitry of a Data Storage Device (DSD) including a NAND memory, the computer- executable instructions cause the control circuitry to:

receive a memory access command from a host to access data in the NAND memory;
identify a location in the NAND memory for performing the memory access command using a Flash Translation Layer (FTL) that has a finer logical-to-physical granularity than a logical-to-physical granularity of a logical block-based file system executed by the host;
and
access the NAND memory at the identified location to perform the memory access command.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

16/246,401Filed 11 Jan 2019 · us provisional application

Priority

1 Oct 2018

Published

US 2020/0104252 A12 Apr 2020

Granted

8 Sep 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 9/5016
The resources being hardware resources other than CPUs, Servers and Terminals: the resource being the memory
G06F 9/5077
Partitioning or combining of resources: logical partitioning of resources; Management or configuration of virtualized resources
G06F 12/08
Addressing or allocation; Relocation: in hierarchically structured memory systems, e.g. virtual memory systems

Fine granularity translation layer for data storage devices

Life of this patent

Fine granularity translation layer for data storage devices

Life of this patent

Abstract

Claims21