Disposable parity
AssigneeMicron Technology, Inc.
InventorGiuseppe Cariello
Life of this patent
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Abstract
Devices and techniques for disposable parity are described herein. First and second portions of data can be obtained, and respective parity values stored in adjacent memory locations. An entry mapping the respective parity values to the first and second portions of data is updated when the parity values are stored. If an error occurs when writing a portion of data, the mapping entry is used to retrieve the parity data to correct the error. Otherwise, the parity data is discarded.
Claims24
An array controller for disposable parity in a NAND device, the array controller comprising:
- a volatile memory;
- and
- processing circuitry to:
- obtain a first portion of data;
- store a first parity value for the first portion of data in a first memory location;
- update a data-to-parity table with a first entry that includes a mapping between the first portion of data and the first memory location;
- obtain a second portion of data;
- store a second parity value for the second portion of data in a second memory location that is adjacent to the first memory location;
- update the data-to-parity table with a second entry that including a mapping between the second portion of data and the second memory location;
- detect an error during a write of the first portion of data;
- use the first parity value via a lookup in the data-to-parity table to correct the error;
- and
- discard the first memory location and second memory location in response to a successful write of the first data portion and the second data portion.
A method for disposable parity in a NAND device, the method comprising:
- obtaining a first portion of data;
- storing a first parity value for the first portion of data in a first memory location;
- updating a data-to-parity table with a first entry that includes a mapping between the first portion of data and the first memory location;
- obtaining a second portion of data;
- storing a second parity value for the second portion of data in a second memory location that is adjacent to the first memory location;
- updating the data-to-parity table with a second entry that including a mapping between the second portion of data and the second memory location;
- detecting an error during a write of the first portion of data;
- using the first parity value via a lookup in the data-to-parity table to correct the error;
- and
- discarding the first memory location and second memory location in response to a successful write of the first data portion and the second data portion.
A machine readable medium including instructions for disposable parity in a NAND device, the instructions, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:
- obtaining a first portion of data;
- storing a first parity value for the first portion of data in a first memory location;
- updating a data-to-parity table with a first entry that includes a mapping between the first portion of data and the first memory location;
- obtaining a second portion of data;
- storing a second parity value for the second portion of data in a second memory location that is adjacent to the first memory location;
- updating the data-to-parity table with a second entry that including a mapping between the second portion of data and the second memory location;
- detecting an error during a write of the first portion of data;
- using the first parity value via a lookup in the data-to-parity table to correct the error;
- and
- discarding the first memory location and second memory location in response to a successful write of the first data portion and the second data portion.
Dependencies are inferred from the claim text.