Memory device that changes a writable region of a data buffer based on an operational state of an ECC circuit

A semiconductor device, comprising:

• a semiconductor memory cell array including memory cells in pages, the memory cells arranged in rows and columns, memory cells in a same column connected to a same bit line, each memory cell in a page being assigned a column address from a continuous sequence of column addresses;
• a controller circuit configured to communicate with a host through a serial interface, to receive write data from the host to be written to the semiconductor memory cell array, and to store the write data in a data buffer before writing the write data to the semiconductor memory cell array as a page, the data buffer storing the write data in a plurality of data segments corresponding to adjacent ranges of column addresses in the continuous sequence of column addresses to which the write data is to be written in the semiconductor memory cell array;
• and
• an error-correcting code (ECC) circuit configured to generate an error correction code for write data stored in each of data segment of the data buffer if the ECC circuit is in a valid state, wherein
• when the ECC circuit is in the valid state and the controller circuit receives a first logical column address and first write data from the host, the controller circuit writes the first write data to a first physical column address of the data buffer, and writes the error correction code generated by the ECC circuit from the first write data to a second physical column address, the second physical column address being located within a first region of the data buffer, wherein data from the host cannot be written into the first region by the controller circuit when the ECC circuit is in the valid state, and the first physical column address being located within a second region of the data buffer, wherein data from the host can be written into the second region by the controller circuit when the ECC circuit is in the valid state, and
• when the ECC circuit is in an invalid state and the controller circuit receives a third logical column address and second write data from the host, the controller circuit writes the second write data to a third physical column address of the data buffer and writes the error correction code generated by the host from the second write data to a fourth physical column address of the data buffer, the third physical column address being located within the second region of the data buffer and the fourth physical column address being located within the first region of the data buffer.

A method of writing write data in a memory device including a semiconductor memory cell array including memory cells in pages, the memory cells arranged in rows and columns, memory cells in a same column connected to a same bit line, each memory cell in a page being assigned a column address from a continuous sequence of column addresses, a controller circuit configured to communicate with a host through a serial interface, to receive write data from the host to be written to the semiconductor memory cell array as a page, and to store the write data in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is in a valid state, said method comprising:

• when the ECC circuit is in the valid state, receiving a first logical column address and a first write data from the host, and writing the first write data to a first physical column address of the data buffer, and writing the error correction code generated by the ECC circuit from the first write data to a second physical column address, the second physical column address being located within a first region of the data buffer, wherein data from the host cannot be written into the first region by the controller circuit when the ECC circuit is in the valid state, and the first physical column address being located within a second region of the data buffer, wherein data from the host can be written into the second region by the controller circuit when the ECC circuit is in the valid state, and
• when the ECC circuit is in the invalid state, receiving a third logical column address and a second write data from the host, and writing the second write data to a third physical column address of the data buffer and writing the error correction code generated by the host from the second write data to a fourth physical column address of the data buffer, the third physical column address being located within the second region of the data buffer and the fourth physical column address being located within the first region of the data buffer.