Dynamic random access memory devices and memory systems having the same

A DRAM device comprising:

• first data terminals through which n-bit first data is input, wherein n is a positive integer;
• a first data strobe signal terminal through which a first data strobe signal is input;
• a first data bus inversion signal terminal through which a first data bus inversion signal is input;
• second data terminals through which n-bit second data is input;
• a second data strobe signal terminal through which a second data strobe signal is input;
• a second data bus inversion signal terminal through which a second data bus inversion signal is input;
• command and address terminals through which a row address or a column address is input;
• a control signal generator configured to detect the first data strobe signal and generate a control signal;
• a cyclic redundancy code (CRC) unit configured to
• perform a first CRC logical operation on a first data group including qn-bit first data and a q-bit first data bus inversion signal generated by sequentially inputting n-bit first data with the first data strobe signal q times, wherein q is a positive integer,
• generate an n-bit first internal CRC,
• compare the first internal CRC and a first CRC,
• generate a first CRC result signal,
• perform a second CRC logical operation on qn-bit second data and a q-bit second data bus inversion signal generated by sequentially inputting n-bit second data with the second data strobe signal q times,
• generate an n-bit second internal CRC,
• compare the second internal CRC and a second CRC,
• generate a second CRC result signal, and
• generate an error signal based on the first CRC result signal and the second CRC result signal in response to the control signal having a first value and generate the error signal based on the second CRC result signal regardless of the first CRC result signal in response to the control signal having a second value;
• a row decoder configured to decode the row address and generate a plurality of word selection signals;
• a column decoder configured to decode the column address and generate a plurality of column selection signals;
• and
• a memory cell array configured to store the qn-bit first data and the qn-bit second data in memory cells selected by the plurality of word selection signals and the plurality of column selection signals or store the qn-bit second data in response to the control signal,
• wherein the first CRC is applied through the first data terminals, and the second CRC is applied through the second data terminals.

A memory system comprising:

• a system board;
• a plurality of DRAM devices installed on the system board;
• and
• a controller installed on the system board and configured to control the plurality of DRAM devices,
• wherein each of the plurality of DRAM devices comprises:
• first terminals through which n-bit first data and a first data strobe signal, which are applied from the controller, are input, wherein n is a positive integer;
• second terminals through which n-bit second data and a second data strobe signal, which are applied from the controller, are input;
• a control signal generator configured to generate a control signal;
• and
• a cyclic redundancy code (CRC) unit configured to
• perform a first CRC logical operation on a first data group comprising qn-bit first data generated by sequentially inputting n-bit first data with the first data strobe signal q times, wherein q is a positive integer,
• generate a first CRC result signal,
• perform a second CRC logical operation on a second data group including qn-bit second data generated by sequentially inputting n-bit second data with the second data strobe signal q times,
• generate a second CRC result signal, and
• generate an error signal based on the first CRC result signal and the second CRC result signal in response to the control signal having a first value and generate the error signal based on the second CRC result signal regardless of the first CRC result signal in response to the control signal having a second value.