Branch instruction

Apparatus for processing data comprising:

• processing circuitry to perform processing operations specified by a sequence of program instructions;
• an instruction decoder to decode said sequence of program instructions to generate control signals to control said processing circuitry to perform said processing operations;
• wherein
• said instruction decoder comprises branch-future instruction decoding circuitry to decode a branch-future instruction, said branch-future instruction having a programmable parameter associated with a branch target address and further programmable branch point data parameter indicative of a predetermined instruction following said branch-future instruction within said sequence of program instructions;
• and
• said processing circuitry comprises branch control circuitry controlled by said branch-future instruction decoding circuitry and responsive to said branch point data to trigger a branch to processing of program instructions starting from a branch target instruction corresponding to said branch target address when processing of said sequence of program instructions reaches said predetermined instruction;
• wherein said branch-future instruction decoder circuitry controls said processing circuitry to store said branch point data and said branch target address in a branch control cache;
• and
• wherein in response to one or more of:
• said processing circuitry being reset;
• loop control circuitry or a loop-end instruction determining that no further iterations of a program loop body are required;
• an exception being entered;
• exception tail-chaining whereby processing proceeds directly from processing a current exception to processing a next exception without restoring state prior to said current exception;
• execution of a branch instruction with greater than a predetermined immediate target address range;
• execution of a branch instruction;
• execution of a loop-start instruction;
• returning from an exception;
• execution of an instruction that causes an instruction cache of said data processing apparatus to be invalidated;
• execution of an instruction that disables caching of said control data;
• execution of an instruction that disables branch prediction;
• said processing circuitry determining that a branch within a program loop body targets an address that is not between a loop-start instruction and a loop-end instruction;
• a switch between a secure mode of operation and a non-secure mode of operation;
• and
• one or more implementation defined conditions;
• said branch point data is invalidated.

A method of processing data comprising:

• performing processing operations specified by a sequence of program instructions;
• decoding said sequence of program instructions to generate control signals to control said performing of said processing operations;
• wherein
• said decoding including decoding a branch-future instruction, said branch-future instruction having programmable parameters respectively associated with a branch target address and branch point data indicative of a predetermined instruction following said branch-future instruction within said sequence of program instructions;
• and
• triggering a branch to processing of program instructions starting from a branch target instruction corresponding to said branch target address when processing of said sequence of program instructions reaches said predetermined instruction;
• wherein,
• said branch point data comprises one or more of:
• address data indicative of an address of said predetermined instruction;
• end data indicative of an address of a last instruction that immediately precedes said predetermined instruction;
• offset data indicative of a distance between said branch-future instruction and said predetermined instruction;
• a proper subset of bits indicative of a memory storage address of said predetermined instruction starting from a least significant bit end of bits of said memory storage address that distinguish between starting storage addresses of instructions;
• remaining size instruction data indicative of a number of instructions remaining to be processed before said predetermined instruction;
• and
• remaining size data indicative of a number of program storage locations remaining to be processed before said predetermined instruction is reached.

A computer program product storing in non-transitory form a computer program for controlling a computer to provide a virtual machine execution environment operating in accordance with a method of processing data comprising:

• performing processing operations specified by a sequence of program instructions;
• decoding said sequence of program instructions to generate control signals to control said performing of said processing operations;
• wherein
• said decoding including decoding a branch-future instruction, said branch-future instruction having programmable parameters respectively associated with a branch target address and branch point data indicative of a predetermined instruction following said branch-future instruction within said sequence of program instructions;
• and
• triggering a branch to processing of program instructions starting from a branch target instruction corresponding to said branch target address when processing of said sequence of program instructions reaches said predetermined instruction;
• wherein,
• said branch point data comprises one or more of:
• address data indicative of an address of said predetermined instruction;
• end data indicative of an address of a last instruction that immediately precedes said predetermined instruction;
• offset data indicative of a distance between said branch-future instruction and said predetermined instruction;
• a proper subset of bits indicative of a memory storage address of said predetermined instruction starting from a least significant bit end of bits of said memory storage address that distinguish between starting storage addresses of instructions;
• remaining size instruction data indicative of a number of instructions remaining to be processed before said predetermined instruction;
• and
• remaining size data indicative of a number of program storage locations remaining to be processed before said predetermined instruction is reached.