Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
AssigneeMicrosoft Technology Licensing, LLC
InventorsDouglas C. Burger, Aaron L. Smith
Life of this patent
Estimating the term…
Abstract
Systems, apparatuses, and methods related to a block-based processor core topology register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include a sharable resource and a programmable composition topology register. The programmable composition topology register can be used to assign a group of the physical processor cores that share the sharable resource.
Claims17
A processor comprising a plurality of physical processor cores for executing a program comprising a plurality of instruction blocks, the processor comprising:
- a branch predictor configured to select a first group of instructions to be speculatively executed by a logical processor;
- and
- a programmable composition topology register for assigning a number of physical processor cores of the plurality of physical processor cores to the logical processor, the programmable composition topology register being dynamically programmable during execution of the program, the composition topology register comprising a composition field and a mode field for specifying a meaning of the composition field, the composition field providing a bit-map of the physical processor cores of the logical processor when the mode field is programmed with a first value, and the composition field providing the number of the physical processor cores of the logical processor when the mode field is programmed with a second value.
A processor comprising a plurality of physical processor cores for executing a plurality of instructions, a respective physical processor core comprising:
- a sharable resource configurable to be shared with a group of physical processor cores of the plurality of physical processor cores, the sharable resource used for executing instructions on the group of physical processor cores;
- and
- a programmable composition topology register for assigning the group of the physical processor cores that share the sharable resource, the programmable composition topology register being dynamically programmable during execution of the program, wherein the group of physical processor cores is programmed using a composition field of the composition topology register that identifies each physical processor core of the group of physical processor cores, and each physical processor core of the group of physical processor cores is identified with a bitmap of the physical processor cores.
A method of executing a program on a processor comprising a first physical processor core and a second physical processor core, the program comprising a plurality of instructions arranged in one or more threads, the method comprising:
- composing a logical processor comprising the first physical processor core and the second physical processor core according to a value stored in a composition topology register, the composition topology register comprising a composition field that identifies each physical processor core of a logical processor using a bitmap of the physical processor cores, the value stored in the composition topology register representing the bitmap of the physical processor cores;
- non-speculatively executing a first set of instuctions of the thread on the first physical processor core;
- and
- speculatively executing a second set of instructions of the thread on the second physical processor core.
Dependencies are inferred from the claim text.