Boosting local memory performance in processor graphics
AssigneeIntel Corporation
InventorCan K. Que
Life of this patent
Estimating the term…
Abstract
In some cases, processor graphics with a slower local memory can compensate by using another memory in place of the lowest level or L3 cache. For example, in some processors, there is a large register space that can be used for the local memory function by allocating the local memory within those registers. Also, since the registers do not operate with barriers, barriers can be simulated by letting one execution unit thread execute more SIMD instructions. For example, one execution thread may simulate a whole work-group in the OpenCL API.
Claims27
A method comprising:
- executing a first work-group on a processor, wherein the first work-group comprises a plurality of work-items that are executed in parallel to perform a defined function, wherein the processor comprises internal registers files, wherein the processor uses a cache hierarchy including a lowest level cache and at least one other cache;
- determining an available space in the internal register files of the processor;
- allocating the determined available space in the internal register files as local memory for the first work-group, wherein the local memory for the first work-group is only accessible by the plurality of work-items included in the first work-group;
- and
- within the available space of the internal register files that is allocated as the local memory for the first work-group, simulating a barrier of the first work-group by controlling a number of single instruction multiple data instructions executed by one execution thread.
One or more non-transitory computer readable media storing instructions to perform a sequence comprising:
- executing a first work-group on a processor, wherein the first work-group comprises a plurality of work-items that are executed in parallel to perform a defined function, wherein the processor comprises internal registers files, wherein the processor uses a cache hierarchy including a lowest level cache and at least one other cache;
- determining an available space in the internal register files of the processor;
- allocating the determined available space in the internal register files as local memory for the first work-group, wherein the local memory for the first work-group is only accessible by the plurality of work-items included in the first work-group;
- and
- within the available space of the internal register files that is allocated as the local memory for the first work-group, simulating a barrier of the first work-group by controlling a number of single instruction multiple data instructions executed by one execution thread.
An apparatus comprising:
- a processor to:
- execute a first work-group comprising a plurality of work-items that are executed in parallel to perform a defined function, wherein the processor comprises internal registers files, wherein the processor uses a cache hierarchy including a lowest level cache and at least one other cache;
- determine an available space in the internal register files of the processor;
- allocate the determined available space in the internal register files as local memory for the first work-group, wherein the local memory for the first work-group is only accessible by the plurality of work-items included in the first work-group;
- and
- within the available space of the internal register files that is allocated as the local memory for the first work-group, simulate a barrier of the first work-group by controlling a number of single instruction multiple data instructions executed by one execution thread;
- and
- a storage coupled to said processor.
Dependencies are inferred from the claim text.