Decoding predicated-loop instruction and suppressing processing in one or more vector processing lanes

Apparatus for processing data comprising:

• processing means for performing processing operations specified by program instructions including at least one vector processing program instruction supporting processing of up to Nmax vector elements associated with respective vector processing lanes;
• an instruction decoding means for decoding said program instructions to generate control signals to control said processing means to perform said processing operations;
• wherein
• said instruction decoding means comprises predicated-loop instruction decoding means for decoding a predicated-loop instruction having associated therewith a number of vector elements Nve to be processed during a number of iterations of a program loop body to be performed;
• and
• said processing means comprises predication loop control means for operating when Nve/Nmax does not equal a whole number at least partially to suppress processing in one or more of said vector processing lanes during one of more of said iterations such that a total number of vector elements processed during said iterations is Nve;
• the apparatus comprising vector storage means for providing vector registers each having a predetermined number of bits VRwidth and able to store a plurality of said vector elements, each of said vector elements having a number of bits VEwidth;
• and
• floating point storage means for storing floating point data values and floating point control storage means for storing floating point control data and a value indicative of VEwidth;
• wherein
• when floating point data values are accessible to said program instructions, said floating point control storage means is also accessible;
• and
• when said floating point data values are inaccessible to said program instructions, said floating point control storage means is also inaccessible.

A method of processing data comprising:

• performing processing operations specified by program instructions including at least one vector processing program instruction supporting processing of up to Nmax vector elements associated with respective vector processing lanes;
• decoding said program instructions to generate control signals to control said performing of said processing operations;
• wherein
• said decoding of said program instructions comprises decoding a predicated-loop instruction having associated therewith a number of vector elements Nve to be processed during a number of iterations of a program loop body to be performed;
• and
• when Nve/Nmax does not equal a whole number, at least partially suppressing processing in one or more of said vector processing lanes during one of more of said iterations such that a total number of vector elements processed during said iterations is Nve;
• wherein the processing operations are performed using processing circuitry comprising vector registers each having a predetermined number of bits VRwidth and able to store a plurality of said vector elements, each of said vector elements having a number of bits VEwidth;
• wherein floating point data values and are stored in floating point registers and floating point control data and a value indicative of VEwidth are stored in a floating point control register;
• when floating point data values stored in floating point registers are accessible to said program instructions, said floating point control register is also accessible;
• and
• when said floating point data values are inaccessible to said program instructions, said floating point control register is also inaccessible.