Processor supporting arithmetic instructions with branch on overflow and methods

A method of instruction-controlled execution in a microprocessor, comprising:

• decoding, in the microprocessor, an instruction into data identifying a first register, a second register, an immediate value, and an opcode identifier;
• and
• interpreting the opcode identifier as indicating that an arithmetic operation is to be performed using data from the first register and the second register, and that the microprocessor is to perform a change of control operation in response to the addition of the first register and the second register causing overflow, wherein the change of control operation is to a location in a program determined based on the immediate value,
• wherein interpreting that the microprocessor is to perform a change of control operation in response to the addition of the first register and the second register causing overflow includes providing a first part of data in the first register and a first part of data in the second register to a first overflow detection circuit, providing a second part of the data in the first register and a second part of the data in the second register to a second overflow detection circuit, and determining that the microprocessor is to perform a change of control operation as a function of a Boolean operation on the outputs of the first overflow detection circuit and the second overflow detection circuit;
• performing the arithmetic operation, generating a signal indicating whether or not the arithmetic operation overflowed, and responsive to the signal indicating overflow, updating a program counter to the location in the program determined based on the immediate value;
• and
• checking for overflow at multiple boundaries within a multi-word arithmetic operation.