Matrix normal/transpose read and a reconfigurable data processor including same

A configurable circuit, comprising:

• a memory array;
• logic to write a matrix to the memory array, the matrix having elements with a data width having a number D of bits of data;
• transpose read logic configurable according to the data width, to output vectors of a transpose read of the matrix;
• and
• normal read logic to output vectors of a normal read of the matrix;
• wherein the memory array includes a plurality of slots, where slots in the plurality of slots include have a slot width (number of columns) equal to a multiple M greater than 1 of the data width.

A reconfigurable data processor, comprising:

• an array of configurable units;
• and
• a bus system connected to the array of configurable units which communicates data at a bus clock rate;
• wherein a configurable unit in the array of configurable units includes:
• a memory array,
• logic to write a matrix to the memory array at the bus clock rate, the matrix having elements with a data width having a number D of bits of data;
• and
• transpose read logic configurable according to the data width, to output vectors of a transpose read of the matrix at the bus clock rate,
• wherein the transpose read logic and the normal read logic are operable on the memory array to output in parallel respective vectors in transposed and normal orders.

A reconfigurable data processor, comprising:

• an array of configurable units;
• and
• a bus system connected to the array of configurable units which communicates data at a bus clock rate;
• wherein a configurable unit in the array of configurable units includes:
• a memory array,
• logic to write a matrix to the memory array at the bus clock rate, the matrix having elements with a data width having a number D of bits of data;
• and
• transpose read logic configurable according to the data width, to output vectors of a transpose read of the matrix at the bus clock rate;
• wherein the memory array includes a plurality of slots, where slots in the plurality of slots include having a slot width (number of columns) equal to a multiple M greater than 1 of the data width.

A memory circuit, comprising:

• a memory array;
• write logic to write a matrix to the memory array, the matrix having elements with a data width having a number D of bits of data, wherein the memory array includes a plurality of slots readable in parallel on different rows, where slots in the plurality of slots have a slot width equal to a multiple M of the data width, with logic to organize, when M is greater than 1, sets of M rows of the matrix in the memory array into a plurality of rows of atoms of M by M elements, so that atoms in a row of atoms are stored in respective slots in the plurality of slots, and rotated in position in the row of atoms relative to an input matrix as a function of a row number of the row of atoms in the plurality of rows of atoms;
• and
• transpose read logic to output vectors of a transpose read of the matrix, including logic to select atoms in the slots, and store the selected atoms in a reshape circuit, the reshape circuit including circuits to transpose the selected atoms to form output vectors of a transpose read of the matrix.

A memory circuit for transpose read of a matrix, comprising:

• memory;
• means for organizing sets of M rows of a matrix into a plurality of slots having a slot width of M elements in the memory into a plurality of rows of atoms of M by M elements, atoms in a row of atoms being stored in respective slots in the memory, and rotated in position in the row of atoms relative to an input matrix as a function of a row number of the row of atoms in the plurality of rows of atoms;
• and
• means for selecting atoms in the slots to be read, and transposing the selected atoms to form output vectors of the transpose read of the matrix.