Efficient modulo calculation
AssigneeImagination Technologies Limited
InventorSimon Fenney
Life of this patent
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AssigneeImagination Technologies Limited
InventorSimon Fenney
Estimating the term…
Hardware logic is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and left-shifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a pre-defined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.
An apparatus comprising hardware logic arranged to perform modulo calculation with respect to a constant value b, the hardware logic comprising a unit arranged to:
A non-transitory computer readable storage medium having stored thereon computer readable instructions that, when processed at a computer system for generating a manifestation of an integrated circuit, cause the computer system to generate a manifestation of an integrated circuit arranged to perform modulo calculation, the integrated circuit comprising a unit arranged to:
A method of manufacturing, using an integrated circuit manufacturing system, an integrated circuit comprising hardware logic arranged to perform modulo calculation with respect to a constant value b, the hardware logic comprising a unit arranged to
Dependencies are inferred from the claim text.