Arithmetic logic unit for single-cycle fusion operations

An arithmetic logic unit for executing arithmetic operations on three binary operands in a single stage of a cycle of a processor, the arithmetic logic unit comprising:

• a first logic circuit for generating a first partial result in a first stage of a single clock cycle of a processor, the first logic circuit having a first part to receive two operands and having a second part to receive a third operand;
• a second logic circuit for generating a second partial result in the first stage of the same single clock cycle of the processor as the first logic circuit, the second logic circuit having a first part to generate a carry-in result for an addition operation and a second part to select a second part result that is a function of at least one of the operands, wherein the second partial result is at least one of the group consisting of the carry-in result and the second part result;
• an adder configured to receive the first partial result from the first logic circuit and the second partial result from the second logic circuit, and further configured to generate a secondary result during a second stage of the same single cycle that the first logic circuit and the second logic circuit generate the first partial result and the second partial result, respectively;
• and
• a backend circuit for generating a final result, wherein the backend circuit performs additional operations on the secondary result in a third stage of the same single cycle of the processor,
• wherein the first logic circuit is configured so that the output of first and second AND gates are the two inputs of a first OR gate, and the output of the first OR gate is a first input to a third AND gate and the output of a NAND gate is connected as one input to a second OR gate and the output of the second OR gate is the second input to the third AND gate, and the output of the third AND gate is connected as the first input to an Exclusive OR gate.

A method of performing arithmetic operations in a computer processor, said method comprising:

• inputting three operands into a first logical circuit;
• generating a first partial result in the first logical circuit in a first stage of a first cycle of the processor;
• generating a second partial result in a second circuit in the first stage of the first cycle of the processor;
• generating a secondary result from the first partial result and the carry result during a second stage of the first cycle of the processor, wherein the secondary result is an arithmetic operation or logical function of the three operands;
• and
• generating a final result by performing additional operations and functions on the secondary result output by an adder during a third stage of the first cycle of the processor.