Processor, information processing apparatus and operation method for processor

An information processing apparatus, comprising:

• a processor;
• and
• a main memory configured to be accessed from the processor;
• wherein the processor includes
• a plurality of processor cores, and
• an internal memory configured to be accessed from the plurality of processor cores,
• wherein an arithmetic unit provided in any of the plurality of processor cores includes
• a regular addition circuit including a first adder and a second register, the first adder being configured to add a plurality of outputs of the plurality of first registers, the second register being configured to be provided in a second stage and latch an output of the first adder,
• an overtaking addition circuit including a second adder, the second adder being configured to add a plurality of outputs of the plurality of first registers, and
• a synthesis circuit including a third adder and a third register, the third adder being configured to add an output of the regular addition circuit and an output of the overtaking addition circuit, the third register being configured to be provided in a third stage and latch an output of the second adder,
• wherein each of the first adder and the second adder is configured to exclusively select and receive a plurality of outputs of the plurality of first registers as inputs thereto, and
• wherein each of the first, second and third registers is configured to latch the inputs thereto in synchronism with a clock.

An operation method for a processor, the processor including a plurality of processor cores and an internal memory, the internal memory being configured to be accessed from the plurality of processor cores, any of the plurality of processor cores having an arithmetic unit, the arithmetic unit including first registers, a regular addition circuit, an overtaking addition circuit, and a synthesis circuit, the first registers being provided in a first stage of the arithmetic circuit, the regular addition circuit including a first adder and a second register, the first adder being configured to add a plurality of outputs of the plurality of first registers, the second register being provided in a second stage of the arithmetic circuit and being configured to latch an output of the first adder, the overtaking addition circuit including a second adder configured to add a plurality of outputs of the plurality of first registers, and the synthesis circuit including a third adder and a third register, the third adder being configured to add an output of the regular addition circuit and an output of the overtaking addition circuit, and the third register being provided in a third stage of the arithmetic unit and being configured to latch an output of the second adder, the operation method comprising:

• causing the first adder and the second adder to exclusively select and receive a plurality of outputs of the plurality of first registers as inputs thereto;
• causing the first, second and third registers to latch inputs thereto in synchronism with a clock;
• causing the first adder to add a single or a plurality of first input data inputted in a first cycle and causing the second register to latch the addition value by the first adder;
• causing the second adder to add a single or a plurality of second input data inputted in a second cycle next to the first cycle;
• and
• causing the third adder to add an output of the regular addition circuit and an output of the overtaking addition circuit and causing the third register to latch the addition value by the third adder.