Memory access for multiple circuit components

An integrated circuit, comprising:

• a memory device;
• a read access engine;
• a write access engine;
• a first port configured to receive first data elements sequentially from the read access engine within a first duration;
• a second port configured to transmit second data elements sequentially to the write access engine within a second duration,
• wherein the read access engine is configured to:
• receive the first data elements from the memory device within a third duration shorter than the first duration;
• and
• transmit, via the first port, the received first data elements to a first processing circuit sequentially within the first duration;
• and wherein the write access engine is configured to:
• receive, via the second port, the second data elements from a second processing circuit sequentially within the second duration;
• and
• store the received second data elements in the memory device within a fourth duration shorter than the second duration.

A method, comprising:

• receiving, from a first circuit in an integrated circuit, a first request for receiving first data;
• performing a read operation at a memory device to receive the first data based on the first request;
• converting the first data into a first sequential data stream;
• transmitting the first sequential data stream to the first circuit;
• receiving, from a second circuit, a second request for storing second data;
• receiving, from the second circuit, a second sequential data stream;
• converting the second sequential data stream into the second data;
• and
• performing a write operation at the memory device to store the second data at the memory device based on the second request.