Technologies for providing shared memory for accelerator sleds

One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause an accelerator sled to:

• receive, with a memory controller coupled to an accelerator device of the accelerator sled, a memory access request from the accelerator device to access a region of memory, wherein the request identifies the region of memory with a logical address;
• determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory;
• and
• route the memory access request to a memory device associated with the determined physical address, wherein the memory access request includes the determined physical address and to route the memory request comprises to send, from the memory controller, the memory access request through a network interface controller of the accelerator sled to a compute sled associated with a workload for which a function is accelerated by the accelerator device.

An accelerator sled comprising:

• circuitry for receiving, by a memory controller coupled to an accelerator device on the accelerator sled, a memory access request from the accelerator device to access a region of memory, wherein the request identifies the region of memory with a logical address;
• means for determining from a map of logical addresses and associated physical address, the physical address associated with the region of memory;
• and
• circuitry for routing, via the memory controller, the memory access request to a memory device associated with the determined physical address, wherein the memory access request includes the determined physical address and routing the memory request includes sending, from the memory controller, the memory access request through a network interface controller of the accelerator sled to a compute sled associated with a workload for which a function is accelerated by the accelerator device.