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US 10,768,828 B2Granted
Data movement between volatile and non-volatile memory in a read cache memory
AssigneeMicron Technology, Inc.
InventorsEugene Feng, Mathew Arcoleo
Life of this patent
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Abstract
The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.
Claims17
A method for operating a memory, comprising:
- receiving a first set of cached data at a dynamic random-access memory (DRAM) array;
- promoting a portion of the first set of cached data to a class of the DRAM array based on a data characteristic of the portion of the first set of cached data;
- promoting a second set of cached data that is in a particular percentage range of most frequently accessed cached data of the cached data that has been accessed more than once from the class of the DRAM array to a first NAND array;
- promoting a third set of cached data to a second NAND array in response to the first NAND array reaching a threshold capacity;
- demoting the cached data of the third set of cached data to the DRAM array in response to the second NAND array reaching a different threshold capacity;
- evicting a fourth set of cached data in the DRAM array in response to the DRAM array receiving a fifth set of cached data, wherein the fourth set of cached data does not meet a threshold requirement to be promoted to the class of the DRAM array, the first NAND array, or the second NAND array, and wherein the threshold requirement includes an access threshold;
- and
- demoting a sixth set of cached data from the first NAND array to the DRAM in response to the sixth set of cached data failing to reach the threshold requirement.
5 more elements
A method for operating a memory, comprising:
- receiving cached data that is in a particular percentage range of most frequently accessed cached data that has been accessed more than once from a DRAM device to a primary NAND device;
- evicting data from the primary NAND device that does not meet a threshold requirement to be promoted to a secondary NAND device in response to receiving the cached data from the DRAM device, wherein the threshold requirement includes an access threshold;
- dynamically marking bad pages within the received cached data;
- promoting a portion of the received cached data from the primary NAND to the secondary NAND in response to the primary NAND device reaching a threshold cached data capacity, and demoting the received cached data to the DRAM device in response to the secondary NAND reaching a different threshold capacity,
- wherein the portion of the received cached data from the primary NAND device does not include the marked bad pages;
- erasing the primary NAND array;
- and
- swapping the primary and the secondary NAND devices such that the primary NAND device becomes a new secondary NAND device and the secondary NAND device becomes a new primary NAND device.
5 more elements
An apparatus, comprising:
- a memory device, comprising:
- a dynamic random-access memory (DRAM);
- and
- a first NAND array and a second NAND array;
- and
- a controller configured to:
- receive a first set of cached data at the DRAM array;
- evict a second set of cached data from the DRAM array that does not meet a threshold requirement to be promoted to a class of the DRAM array, a first NAND array, or a second NAND array in response to receiving the first set of cached data, wherein the threshold requirement includes an access threshold;
- promote a portion of the first set of cached data to the class of the DRAM array based on a data characteristic of the portion of the first set of cached data;
- promote a third set of cached data that is in a particular percentage range of most frequently accessed cached data that has been accessed more than once from the class of the DRAM array to the first NAND array;
- promote a fourth set of cached data to the second NAND array in response to the first NAND array reaching a threshold capacity;
- demote the cached data of the fourth set of cached data to the DRAM array in response to the second NAND array reaching a different threshold capacity;
- and
- demote a fifth set of cached data from the first NAND array to the DRAM in response to the fifth set of cached data failing to reach the threshold requirement.
11 more elements
Dependencies are inferred from the claim text.