Stacked memory device and a memory chip including the same

A stacked memory device, comprising:

• a logic semiconductor die including a global processor configured to perform a global sub process corresponding to a portion of a data process;
• and
• a plurality of memory semiconductor dies stacked vertically, the memory semiconductor dies including a plurality of local processors configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits configured to store data associated with the data process, wherein each of the memory integrated circuits includes a sense amplifier configured to sense data to be read from the memory integrated circuit and the local processor is separated from the memory integrated circuit on each of the memory semiconductor dies,
• wherein the global processor includes a selector and an arithmetic logic unit, the selector including multiplexers configured to select and provide at least one of internal data provided from a first memory integrated circuit and external data provided from an external device, and wherein the arithmetic logic unit generates an address to access a second memory integrated circuit based on an output of the selector.

A memory device, comprising:

• a logic semiconductor die including a global processor configured to perform a global sub process corresponding to a first portion of a data process of an external device;
• and
• a plurality of memory semiconductor dies, wherein the memory semiconductor dies are stacked with respect to each other and a first memory semiconductor die includes a first local processor configured to perform a local sub process corresponding to a second portion of the data process and a memory integrated circuit configured to store data associated with the data process, wherein the memory integrated circuit includes a sense amplifier configured to sense data to be read from the memory integrated circuit and the first local processor is separated from the memory integrated circuit on the first memory semiconductor die,
• wherein the global processor includes a selector and an arithmetic logic unit, the selector including multiplexes configured to select and provide at least one of internal data provided from the memory integrated circuit and external data provided from the external device, and wherein the arithmetic logic unit generates an address to access the memory integrated circuit based on an output of the selector.