Arithmetic processing device, information processing apparatus, and method for controlling arithmetic processing device

An information processing apparatus comprising:

• an arithmetic processing device;
• and a host processing device coupled to the arithmetic processing device, the arithmetic processing device includes;
• a communication interface configured to transmit a data request corresponding to a data request instruction stored in a data request queue that stores the data request instruction as an entry and to receive data corresponding to the transmitted data request and an operation instruction;
• and
• a processor including a plurality of computing cores configured to perform an operation by using the data received by the communication interface,
• the processor is configured to:
• determine whether there is no entry in the data request queue;
• determine, when determining that there is no entry in the data request queue, whether one or more computing cores, which is to execute the operation instruction, are during execution by refereeing to a plurality of memories which are provided for the respective computing cores and store information indicating whether the respective computing cores are during execution;
• and
• cause the communication interface to transition to a power-saving state when at least one of the one or more computing cores are during execution.

A method of controlling an arithmetic processing device comprising:

• transmitting, by a communication interface provided in the arithmetic processing device, a data request corresponding to a data request instruction stored in a data request queue that stores the data request instruction as an entry;
• receiving data corresponding to the transmitted data request and an operation instruction;
• performing, by a processor including a plurality of computing cores and provided in the arithmetic processing device, an operation by using the data received by the communication interface;
• determining whether there is no entry in the data request queue;
• determining, when determining that there is no entry in the data request queue, whether one or more computing cores, which is to execute the operation instruction, are during execution by refereeing to a plurality of memories which are provided for the respective computing cores and store information indicating whether the respective computing cores are during execution;
• and
• causing, by the processor, the communication interface to transition to a power-saving state when at least one of the one or more computing cores are during execution.