Co-optimization of lithographic and etching processes with complementary post exposure bake by laser annealing

A method of co-optimizing lithographic and etching processes for semiconductor fabrication, the method comprising:

• determining a first set of locations for first complementary laser annealing to be performed on at least a first semiconductor wafer of a plurality of semiconductor wafers;
• prior to a first post-exposure baking process being performed on at least the first semiconductor wafer, performing the first complementary laser annealing at the first set of locations on at least the first semiconductor wafer;
• after an etching process has been performed on at least the first semiconductor wafer, determining, a second set of locations for a second complementary laser annealing to be performed on at least a second semiconductor wafer of the plurality of semiconductor wafers;
• and
• prior to a second post-exposure baking process being performed on at least the second semiconductor wafer, performing the second complementary laser annealing at the second set of locations on at least the second semiconductor wafer.

A system for co-optimizing lithographic and etching processes for semiconductor fabrication, the system comprising:

• memory;
• one or more processors;
• and
• at least one controller configured to perform a method comprising
• determining a first set of locations for a first complementary laser annealing to be performed on at least a first semiconductor wafer of a plurality of semiconductor wafers;
• performing the first complementary laser annealing at the first set of locations on at least the first semiconductor wafer, wherein the first complementary laser annealing is performed one of before or after a first post-exposure baking process for at least the first semiconductor wafer;
• after an etching process has been performed on at least the first semiconductor wafer, determining, a second set of locations for a second complementary laser annealing to be performed on at least a second semiconductor wafer of the plurality of semiconductor wafers;
• and
• performing the second complementary laser annealing at the second set of locations on at least the second semiconductor wafer, wherein the second complementary laser annealing is performed one of before or after a second post-exposure baking process for at least the second semiconductor wafer.