Enabling thermal efficiency on a silicon-on-insulator (SOI) platform

An apparatus, comprising:

• a base semiconductor layer;
• an insulator layer disposed on the base semiconductor layer, the insulator layer comprising an etched-out portion, which forms a hollow aperture within the insulator layer;
• a silicon-on-insulator (SOI) layer disposed on the insulator layer and comprising a top surface, a bottom surface, and a waveguide, the etched-out portion of the insulator layer being positioned adjacent to the bottom surface of the SOI layer, the top surface of the SOI layer being etched out to form the waveguide such that the waveguide is positioned above the etched-out portion of the insulator layer, a width of the etched-out portion being greater than or equal to a width of the waveguide;
• and
• a polysilicon layer disposed on the SOI layer.

A photonic integrated circuit (PIC) for an optical device, comprising:

• a base semiconductor layer;
• an insulator layer disposed on the base semiconductor layer, the insulator layer comprising an etched-out portion, which forms a hollow aperture within the insulator layer;
• and
• a silicon-on-insulator (SOI) layer disposed on the insulator layer and comprising a top surface, a bottom surface, and a waveguide, the SOI layer comprising a slot laterally-adjacent to the waveguide, the top surface of the SOI layer being etched out to form the waveguide such that the waveguide is positioned above the etched-out portion of the insulator layer, the etched-out portion of the insulator layer being positioned adjacent the bottom surface of the SOI layer, a width of the etched-out portion being greater than or equal to a width of the waveguide.