US 10,768,231 B2Granted

Diagnosing failing scan chains in a semiconductor integrated circuit

AssigneeTeseda Corporation

InventorTheodore Clifton Bernard

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Abstract

“Shoot-through” timing failures in a scan chain of a defective semiconductor integrated circuit corrupt test pattern data used to perform failure analysis. Methods and procedures are provided to detect “shoot-through” conditions, determine the number of shoot-through scan cells, and to determine the location of the shoot-through cells within a scan chain. Reset test pattern results can be analyzed to identify candidate locations of shoot-through cells and when combined with candidate cell locations from analysis of physical clock distribution trees and potential clock-skew issues, the exact location of all shoot-through cells can be determined. Methods are also provided to use shoot-through cell locations to identify the defective clock net containing the physical defect causing the clock skew conditions needed to produce shoot-through timing failures.

Claims14

Dependent claims

A system comprising:

a fixture for receiving a semiconductor integrated circuit device under test (DUT), arranged to provide electrical connection to at least some pins of the DUT;
an IC tester hardware system arranged for connection to the fixture for testing a DUT while mounted in the fixture;
an analysis computer having a network interface for communications with the IC tester;
the analysis computer further including a data interface for communications with a datastore;
the analysis computer further including a user interface for communications with a user interface device;
a datastore operatively coupled to the data interface and storing data files comprising test setups and flush test patterns and reset test patterns for use by the analysis computer in controlling the IC tester;
a computer-readable medium (CRM) storing instructions executable on the analysis computer for operating the IC tester for testing the DUT;
the stored instructions, upon execution, operable to cause the analysis computer, utilizing the IC tester, to—
identify a scan chain in the DUT;
determine whether a shoot-through condition exists in the scan chain,
determine a number of shoot-through cells in the scan chain using at least one of a flush test pattern and a reset test pattern.

8 more elements

A non-volatile computer-readable medium storing instructions executable on a processor to test a semiconductor integrated circuit device under test (DUT), the stored instructions, upon execution, operable to cause the processor to—

select a scan chain in the DUT;
and
determine a number of shoot-through cells in the scan chain using at least one of a flush test pattern and a reset test pattern.

A method for testing a scan chain of a semiconductor integrated circuit, the method comprising the steps of:

determining locations of shoot-through cells in the scan chain by—
applying reset pattern analysis to determine one or more candidate ranges, each candidate range extending zero or more cells from an initial candidate shoot-through cell, backwards in the scan chain, so as to include all cells with the same expected value as the initial candidate, the candidate ranges together defining a first set of potential shoot-through locations;
storing in memory the first set of candidate ranges of potential shoot-through locations.

Dependencies are inferred from the claim text.

Facts

Application: 16/279,909Filed 19 Feb 2019 · continuation
Priority: 10 Nov 2016
Published: US 2019/0178935 A113 Jun 2019
Granted: 8 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G01R 31/3177
Testing of digital circuits: testing of logic operation, e.g. by logic analysers
G01R 31/31703
Testing of digital circuits: comparison aspects, e.g. signature analysis, comparators
G01R 31/31725
Testing of digital circuits: timing aspects, e.g. clock distribution, skew, propagation delay
G01R 31/318566
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: comparators; Diagnosing the device under test

Family

Application62/420,092Us provisional application · filed 10 Nov 2016
Application15/810,607Parent of this continuation · filed 13 Nov 2017
US 2019/0178935 A1Pre-grant publication · published 13 Jun 2019
US 10,247,777 B1Parent of this continuation
US 10,768,231 B2This patent

From the US filing history. Foreign family members aren’t listed.

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