Built-in device testing of integrated circuits

A system comprising:

• a memory;
• a processor system communicatively coupled to the memory;
• a device under test, the device under test comprising an adaptive testing microcontroller;
• the adaptive testing microcontroller configured to perform a method comprising:
• loading a testing program from the processor system;
• executing the testing program, wherein the testing program is arranged to adjust one or more of the following parameters of the device under test:
• on-chip scan configuration, chip clock skew, voltage regulators, voltage pumps, level shifters, OCCG (On Chip Clock Generators), PLLs (Phase Lock Loops), timing circuits, and elastic I/O DLLs (Chip Input/Output Driver & Receiver Delay Lock Loops);
• receiving, by the microcontroller within the device under test, results from the testing program;
• wherein dynamically adjusting the testing program comprises adjusting one or more of the following parameters of the device under test that are not accessible by external testers:
• on-chip scan configuration, chip clock skew, voltage regulators, voltage pumps, level shifters, OCCG (On Chip Clock Generators), PLLs (Phase Lock Loops), timing circuits, and elastic I/O DLLs (Chip Input/Output Driver & Receiver Delay Lock Loops) and wherein dynamically adjusting the testing program based on the results of the testing program comprises determining that a desired result was not achieved by the results of the testing program;
• and
• executing the adjusted testing program.

A computer program product comprising:

• a computer-readable storage medium having program instructions embodied therewith, wherein the computer-readable storage medium is not a transitory signal, the program instructions readable by a processor system to cause the processor system to perform a method comprising:
• loading a testing program from the processor system for execution by a microcontroller within a device under test;
• executing, by the microcontroller within the device under test, the testing program, wherein the testing program is arranged to adjust one or more of the following parameters of the device under test:
• on-chip scan configuration, chip clock skew, voltage regulators, voltage pumps, level shifters, partial-good configurations, redundancy selections, OCG (On Chip Clock Generators), PLLs (Phase Lock Loops), timing circuits, and elastic I/O DLLs (Chip Input/Output Driver & Receiver Delay Lock Loops);
• receiving results from the testing program;
• dynamically adjusting, by the microcontroller within the device under test, the testing program based on the results of the testing program, wherein dynamically adjusting the testing program comprises adjusting one or more of the following parameters of the device under test that are not accessible by external testers:
• on-chip scan configuration, chip clock skew, voltage regulators, voltage pumps, level shifters, partial-good configurations, redundancy selections, OCG (On Chip Clock Generators), PLLs (Phase Lock Loops), timing circuits, and elastic I/O DLLs (Chip Input/Output Driver & Receiver Delay Lock Loops) and wherein dynamically adjusting the testing program based on the results of the testing program comprises determining that a desired result was not achieved by the results of the testing program;
• and
• executing the adjusted testing program.