Systems and methods for analyzing failure rates due to soft/hard errors in the design of a digital electronic device

A method for analyzing failure rates due to soft/hard errors in the design of a digital electronic device, comprising:

• creating an error injection point by introducing a fault into a code path having a plurality of levels;
• determining an error detection point at which the introduced fault becomes detectable;
• creating a list of all of the logic cells forming the cone of logic that forms the data input to the error detection point, thereby generating a first logic cone list;
• creating a list of all of the logic cells forming the cone of logic that forms the data input to the error injection point, thereby generating a second logic cone list;
• determining the intersection between the first and second logic cone lists;
• and
• conducting a failure rate analysis on the intersection between the first and second logic cone lists by:
• creating, on a computational device, a list of the storage elements in the intersection, thereby generating a storage element list;
• defining a storage element FIT counter;
• for each storage element in the storage element list,
• (a) reading the storage element,
• (b) adding the FIT rate of the storage element to the storage element FIT counter,
• (c) creating a list of all of the logic cells forming the cone of logic that forms the data input to the storage element, thereby generating a logic cone list,
• (d) for each cell in the logic cone list associated with the storage element,
• (i) reading the cell, and
• (ii) if the cell is a pass-through cell, then adding the FIT rate to the storage element FIT counter, and otherwise adding ½ of the FIT rate to the storage element FIT counter,
• (e) computing the clock ratio for the storage element,
• (f) determining the product of the clock ratio and the storage element FIT counter, and
• (g) adding the product to the storage element FIT counter;
• and
• after all of the storage elements in the storage element list have been read, outputting the value of the storage element FIT counter as the failure rate of the design.