Testing mechanism for a proximity fail probability of defects across integrated chips
AssigneeInternational Business Machines Corporation
InventorsKirk D. Peterson, Alain G. Rwabukamba, Andrew A. Turner
Life of this patent
Estimating the term…
Abstract
According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.
Claims16
A method for determining a status of circuitry within a chip by a testing mechanism, the method comprising:
- collecting, by the testing mechanism, fail signatures from portions of the circuitry within the chip to determine the status of the circuitry within a chip, where the fail signatures evidence lack of operability for the portions of the circuitry within the chip;
- analyzing, by the testing mechanism, the fail signatures on a by-level basis to identify a high probability defect area within the chip by statistically determining by-level fail probabilities based on a plurality of signal types of the fail signatures, by associating confidence scores with the by-level fail probabilities, and by determining the chip to be a bad chip with respect to whether the by-level fail probabilities and the confidence scores indicate the status of the circuitry to be bad;
- determining, by the testing mechanism, whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip;
- and
- determining, by the testing mechanism, the status of the circuitry in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.
A computer program product, the computer program product comprising a computer readable storage medium having program instructions of a testing mechanism for determining a status of circuitry within a chip embodied therewith, the program instructions executable by a processor to cause the processor to perform:
- collecting, by the testing mechanism, fail signatures from portions of the circuitry within the chip to determine the status of the circuitry within a chip, where the fail signatures evidence lack of operability for the portions of the circuitry within the chip;
- analyzing the fail signatures on a by-level basis to identify a high probability defect area within the chip by statistically determining by-level fail probabilities based on a plurality of signal types of the fail signatures, by associating confidence scores with the by-level fail probabilities, and by determining the chip to be a bad chip with respect to whether the by-level fail probabilities and the confidence scores indicate the status of the circuitry to be bad;
- determining whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip;
- and
- determining the status of the circuitry in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.
A system, comprising a processor and a memory storing program instructions of testing mechanism for determining a status of circuitry within a chip thereon, the program instructions executable by a processor to cause the system to perform:
- collecting, by the testing mechanism, fail signatures from portions of the circuitry within the chip to determine the status of the circuitry within a chip, where the fail signatures evidence lack of operability for the portions of the circuitry within the chip;
- analyzing the fail signatures on a by-level basis to identify a high probability defect area within the chip by statistically determining by-level fail probabilities based on a plurality of signal types of the fail signatures, by associating confidence scores with the by-level fail probabilities, and by determining the chip to be a bad chip with respect to whether the by-level fail probabilities and the confidence scores indicate the status of the circuitry to be bad;
- determining whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip;
- and
- determining the status of the circuitry in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.
Dependencies are inferred from the claim text.