Semiconductor device and memory module including the semiconductor device

A semiconductor device comprising:

• a plurality of chips configured to check parity bits of a plurality of pattern signals and store test result signals generated by the checking of the parity bits, and configured to output an error detection signal when an error is detected from any of the test result signals;
• and
• a test pad configured to output the error detection signal received from the plurality of chips to an external part,
• wherein the plurality of chips is commonly coupled to at least one connection line such that, when the error detection signal is output from at least one of the plurality of chips, the outputted error detection signal is output through the test pad,
• wherein the plurality of pattern signals include a predetermined number of activated bits,
• wherein each of the plurality of chips includes:
• a buffer circuit configured to buffer a command, an address, at least one chip ID signal, and a chip selection signal, and configured to output the plurality of pattern signals in response to a test signal;
• a parity check circuit configured to output the test result signals and the error detection signal by checking parity bits of the plurality of pattern signals;
• a storage circuit configured to store the test result signals therein;
• and
• a register configured to store an output signal of the storage circuit, and output stored test information to an external part during a read operation.