Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure

A method for testing a vertical memory structure disposed on a semiconductor substrate, the method comprising:

• creating, from a wafer containing a plurality of 3D memory devices, including at least one direct connect 3D memory device;
• wherein some of the plurality of 3D memory devices include peripheral circuitry interconnects disposed over a first 3D memory structure comprising strings of memory cells arranged in an array and coupled between word lines and bit lines;
• wherein the at least one direct connect 3D memory device has no peripheral circuitry interconnects, and is disposed over a second 3D memory structure constructed the same as the first 3D memory structure comprising the strings of memory cells arranged in the array and coupled between the word lines and the bit lines of the some of the plurality of 3D memory devices;
• wherein the step of creating includes providing a testing interconnect structure including test pads over the second 3D memory structure of the at least one direct connect 3D memory device that allows direct electrical connections to the word lines and the bit lines associated therewith;
• directly connecting a direct tester to predetermined ones of the test pads of the at least one direct connect 3D memory device;
• and
• using the direct tester, applying a predetermined voltage to the at least one direct connect 3D memory device to test the electrical integrity of the second 3D memory structure of the at least one direct connect 3D memory device.