US 10,763,853 B2Granted

Multi-mode power management circuit

AssigneeTexas Instruments Incorporated

InventorsWang Li, Qiong M. Li, Yipeng Su

Life of this patent

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Abstract

In an example, a circuit comprising a first inductor coupled between a first node and a second node, a first PMOS having a source terminal coupled to the second node and a drain terminal coupled to a third node, a second PMOS having a source terminal coupled to a ground voltage potential and a drain terminal coupled to the second node, a third PMOS having a source terminal coupled to a fourth node and a drain terminal coupled to the third node, a fourth PMOS having a source terminal coupled to the ground voltage potential and a drain terminal coupled to the fourth node, a NMOS having a source terminal coupled to the third node and a drain terminal coupled to a fifth node, a second inductor coupled between the fourth node and the fifth node, and a controller.

Claims20

Dependent claims

A circuit, comprising:

a first inductor having a first terminal configured to couple to a first node and a second terminal configured to couple to a second node;
a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a source terminal coupled to the second node and a drain terminal coupled to a third node;
a second PMOS having a source terminal coupled to a ground voltage potential and a drain terminal coupled to the second node;
a third PMOS having a source terminal coupled to a fourth node and a drain terminal coupled to the third node;
a fourth PMOS having a source terminal coupled to the ground voltage potential and a drain terminal coupled to the fourth node;
a n-type MOSFET (NMOS) having a source terminal coupled to the third node and a drain terminal coupled to a fifth node;
a second inductor having a first terminal configured to couple to the fourth node and a second terminal configured to couple to the fifth node;
and
a controller coupled to a gate terminal of the first PMOS, a gate terminal of the second PMOS, a gate terminal of the third PMOS, a gate terminal of the fourth PMOS, and a gate terminal of the NMOS.

6 more elements

A system, comprising:

a circuit, comprising:
a first resistor configured to couple between a first node and a second node;
a first inductor coupled between the second node and the third node;
a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a source terminal coupled to the third node and a drain terminal coupled to a fourth node;
a second PMOS having a source terminal coupled to a ground voltage potential and a drain terminal coupled to the third node;
a third PMOS having a source terminal coupled to a fifth node and a drain terminal coupled to the fourth node;
a fourth PMOS having a source terminal coupled to the ground voltage potential and a drain terminal coupled to the fifth node;
a n-type MOSFET (NMOS) having a source terminal coupled to the fourth node and a drain terminal coupled to a sixth node;
a second inductor having a first terminal configured to couple to the fifth node and a second terminal configured to couple to the sixth node;
and
a controller coupled to a gate terminal of the first PMOS, a gate terminal of the second PMOS, a gate terminal of the third PMOS, a gate terminal of the fourth PMOS, and a gate terminal of the NMOS;
a load configured to couple to the fourth node;
and
a battery configured to couple between the sixth node and the ground voltage potential.

11 more elements

A circuit, comprising:

a first inductor having a first terminal configured to couple to a first node and a second terminal configured to couple to a second node;
a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a source terminal coupled to the second node and a drain terminal coupled to a third node;
a second PMOS having a source terminal coupled to a ground voltage potential and a drain terminal coupled to the second node;
a third PMOS having a source terminal coupled to a fourth node and a drain terminal coupled to the third node;
a fourth PMOS having a source terminal coupled to the ground voltage potential and a drain terminal coupled to the fourth node;
a fifth PMOS having a source terminal coupled to a fifth node and a drain terminal coupled to the third node;
a n-type MOSFET (NMOS) having a source terminal coupled to the fourth node and a drain terminal coupled to a sixth node;
a second inductor having a first terminal configured to couple to the fourth node and a second terminal configured to couple to the sixth node;
and
a controller coupled to a gate terminal of the first PMOS, a gate terminal of the second PMOS, a gate terminal of the third PMOS, a gate terminal of the fourth PMOS, a gate terminal of the fifth PMOS, and a gate terminal of the NMOS.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/137,326Filed 20 Sep 2018 · us provisional application
Priority: 2 Oct 2017
Published: US 2019/0103752 A14 Apr 2019
Granted: 1 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H03K 17/6871
The devices being field-effect transistors: the output circuit comprising more than one controlled field-effect transistor
H02J 7/865
Circuit arrangements for charging or discharging batteries or for supplying loads from batteries: battery or charger load switching, e.g.…
H02M 3/1582
Including plural semiconductor devices as final control devices for a single load: buck-boost converters
H03K 17/667
The output circuit comprising more than one controlled bipolar transistor: using complementary bipolar transistors