Counter circuitry and method

Apparatus comprising:

• means for generating a master count signal in response to a clock signal;
• means for generating a slave count signal in response to the clock signal;
• and
• means for providing signal communication between the means for generating a master count signal and the means for generating a slave count signal;
• the means for generating a master count signal being operable to provide to the means for generating a slave count signal via the means for providing signal communication:
• (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value, wherein the means for generating a master count signal is configured to provide the data indicative of the count offset value before providing the timing signal, wherein the data indicative of the count offset value indicates a future count value applicable at a time that the timing signal is provided to the slave counter circuitry;
• and
• the means for generating a slave count signal being operable, during a synchronisation operation for that means for generating a slave count signal, to initialise a counting operation of that means for generating a slave count signal in response to the data indicative of the count offset value and the timing signal provided by the means for generating a master count signal.

A method comprising:

• master counter circuitry generating a master count signal in response to a clock signal;
• the master counter circuitry providing to slave counter circuitry via a synchronisation connection:
• data indicative of a count offset value and a timing signal defining a timing relationship between the clock signal and the count offset value, wherein the master counter circuitry provides the data indicative of the count offset value before providing the timing signal wherein the data indicative of the count offset value indicates a future count value applicable at a time that the timing signal is provided to the slave counter circuitry;
• the slave counter circuitry, during a synchronisation operation for that slave counter circuitry, initialising a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and the timing signal provided by the master counter circuitry;
• and
• the slave counter circuitry generating a slave count signal in response to the clock signal.