Hybrid FinFET structure

A semiconductor device comprising:

• a first active area having a first fin field effect transistor (FinFET) device formed therein, the first FinFET device comprising a plurality of non-planar fins formed in a substrate, an epitaxial layer formed on the plurality of non-planar fins forming first source/drain regions, a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are configured to traverse across the plurality of non-planar fins;
• a second active area having a second FinFET device formed therein, the second FinFET device comprising a planar fin formed in the substrate, wherein the epitaxial layer is formed on the planar fin to form second source/drain regions, and a third gate structure, wherein the third gate structure is configured to traverse across the planar fin, wherein a first spacing between the first gate structure and the second gate structure is less than a second spacing between the second gate structure and the third gate structure;
• and
• a contact, the contact is formed on the epitaxial layer formed over the planar fin between the second gate structure and the third gate structure, wherein the epitaxial layer is silicon phosphorous (SiP).

A semiconductor device comprising:

• a first fin field effect transistor (FinFET) device, the first FinFET device comprising a plurality of non-planar fins extending from a substrate, an epitaxial layer formed on the plurality of non-planar fins forming first source/drain regions, a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are configured to traverse across the plurality of non-planar fins;
• and
• a second FinFET device, the second FinFET device comprising a planar fin extending from the substrate, wherein the a first epitaxial layer is formed on the planar fin to form second source/drain regions, and a third gate structure, wherein the third gate structure is configured to traverse across the planar fin,
• wherein a first bottom surface of an epitaxial layer formed on the planar fin of the second FinFET device is lower than a second bottom surface of an epitaxial layer formed on the plurality of non-planar finds of the first FinFET device,
• wherein the planar fin has a first width in a direction parallel to the first gate structure, and wherein each of the plurality of non-planar fins has a second width in a direction parallel to the third gate structure, wherein the first width is greater than the second width.